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本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many Designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽：
Verilog
verilog
System
VHDL
上傳時(shí)間：
2013-10-16
上傳用戶(hù)：牛布牛
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One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog Designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
標(biāo)簽：
Verilog
編碼
非阻塞性賦值
上傳時(shí)間：
2013-10-17
上傳用戶(hù)：tb_6877751
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CAM350 為PCB 設(shè)計(jì)和PCB 生產(chǎn)提供了相應(yīng)的工具（CAM350 for PCB Designers 和CAM350 for CAM Engineers），很容易地把PCB設(shè)計(jì)和PCB生產(chǎn)融合起來(lái)。CAM350 v8.7的目標(biāo)是在PCB設(shè)計(jì)和PCB制造之間架起一座橋梁隨著如今電子產(chǎn)品的朝著小體積、高速度、低價(jià)格的趨勢(shì)發(fā)展，導(dǎo)致了設(shè)計(jì)越來(lái)越復(fù)雜，這就要求精確地把設(shè)計(jì)數(shù)據(jù)轉(zhuǎn)換到PCB生產(chǎn)加工中去。CAM350為您提供了從PCB設(shè)計(jì)到生產(chǎn)制程的完整流程，從PCB設(shè)計(jì)數(shù)據(jù)到成功的PCB生產(chǎn)的轉(zhuǎn)化將變得高效和簡(jiǎn)化。基于PCB制造過(guò)程，CAM350為PCB設(shè)計(jì)和PCB生產(chǎn)提供了相應(yīng)的工具（CAM350 for PCB Designers和CAM350 for CAM Engineers），很容易地把PCB設(shè)計(jì)和PCB生產(chǎn)融合起來(lái)。平滑流暢地轉(zhuǎn)換完整的工程設(shè)計(jì)意圖到PCB生產(chǎn)中提高PCB設(shè)計(jì)的可生產(chǎn)性，成就成功的電子產(chǎn)品為PCB設(shè)計(jì)和制造雙方提供有價(jià)值的橋梁作用CAM350是一款獨(dú)特、功能強(qiáng)大、健全的電子工業(yè)應(yīng)用軟件。DOWNSTREAM開(kāi)發(fā)了最初的基于PCB設(shè)計(jì)平臺(tái)的CAM350，到基于整個(gè)生產(chǎn)過(guò)程的CAM350并且持續(xù)下去。CAM350功能強(qiáng)大，應(yīng)用廣泛，一直以來(lái)它的信譽(yù)和性能都是無(wú)與倫比的。 CAM350PCB設(shè)計(jì)的可制造性分析和優(yōu)化工具今天的PCB 設(shè)計(jì)和制造人員始終處于一種強(qiáng)大的壓力之下，他們需要面對(duì)業(yè)界不斷縮短將產(chǎn)品推向市場(chǎng)的時(shí)間、品質(zhì)和成本開(kāi)銷(xiāo)的問(wèn)題。在48 小時(shí)，甚至在24 小時(shí)內(nèi)完成工作更是很平常的事，而產(chǎn)品的復(fù)雜程度卻在日益增加，產(chǎn)品的生命周期也越來(lái)越短，因此，設(shè)計(jì)人員和制造人員之間協(xié)同有效工作的壓力也隨之越來(lái)越大！隨著電子設(shè)備的越來(lái)越小、越來(lái)越復(fù)雜，使得致力于電子產(chǎn)品開(kāi)發(fā)每一個(gè)人員都需要解決批量生產(chǎn)的問(wèn)題。如果到了完成制造之后發(fā)現(xiàn)設(shè)計(jì)失敗了，則你將錯(cuò)過(guò)推向市場(chǎng)的大好時(shí)間。所有的責(zé)任并不在于制造加工人員，而是這個(gè)項(xiàng)目的全體人員。多年的實(shí)踐已經(jīng)證明了，你需要清楚地了解到有關(guān)制造加工方面的需求是什么，有什么方面的限制，在PCB設(shè)計(jì)階段或之后的處理過(guò)程是什么。為了在制造加工階段能夠協(xié)同工作，你需要在設(shè)計(jì)和制造之間建立一個(gè)有機(jī)的聯(lián)系橋梁。你應(yīng)該始終保持清醒的頭腦，記住從一開(kāi)始，你的設(shè)計(jì)就應(yīng)該是容易制造并能夠取得成功的。CAM350 在設(shè)計(jì)領(lǐng)域是一個(gè)物有所值的制造分析工具。CAM350 能夠滿(mǎn)足你在制造加工方面的需求，如果你是一個(gè)設(shè)計(jì)人員，你能夠建立你的設(shè)計(jì)，將任務(wù)完成后提交給產(chǎn)品開(kāi)發(fā)過(guò)程中的下一步工序。現(xiàn)在采用CAM350，你能夠處理面向制造方面的一些問(wèn)題，進(jìn)行一些簡(jiǎn)單地處理，但是對(duì)于PCB設(shè)計(jì)來(lái)說(shuō)是非常有效的，這就被成為"可制造性(Manufacturable)"。可制造性設(shè)計(jì)(Designing for Fabrication)使用DFF Audit，你能夠確保你的設(shè)計(jì)中不會(huì)包含任何制造規(guī)則方面的沖突(Manufacturing Rule Violations)。DFF Audit 將執(zhí)行超過(guò)80 種裸板分析檢查，包括制造、絲印、電源和地、信號(hào)層、鉆孔、阻焊等等。建立一種全新的具有藝術(shù)特征的Latium 結(jié)構(gòu)，運(yùn)行DFF Audit 僅僅需要幾分鐘的時(shí)間，并具有很高的精度。在提交PCB去加工制造之間，就能夠定位、標(biāo)識(shí)并立刻修改所有的沖突，而不是在PCB板制造加工之后。DFF Audit 將自動(dòng)地檢查酸角(acid traps)、阻焊條(soldermask slivers)、銅條(copper slivers)、殘缺熱焊盤(pán)(starved thermals)、焊錫搭橋(soldermask coverage)等等。它將能夠確保阻焊數(shù)據(jù)的產(chǎn)生是根據(jù)一定安全間距，確保沒(méi)有潛在的焊錫搭橋的條件、解決酸角(Acid Traps)的問(wèn)題，避免在任何制造車(chē)間的CAM部門(mén)產(chǎn)生加工瓶頸。
標(biāo)簽：
CAM
350
使用說(shuō)明
上傳時(shí)間：
2013-11-23
上傳用戶(hù)：四只眼
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Abstract: Specifications such as noise, effective number of bits (ENOB), effective resolution, and noise-free resolution inlarge part define how accurate an ADC really is. Consequently, understanding the performance metrics related to noise isone of the most difficult aspects of transitioning from a SAR to a delta-sigma ADC. With the current demand for higherresolution, Designers must develop a better understanding of ADC noise, ENOB, effective resolution, and signal-to-noiseratio (SNR). This application note helps that understanding.
標(biāo)簽：
ENOB
模數(shù)轉(zhuǎn)換器
上傳時(shí)間：
2013-10-16
上傳用戶(hù)：x18010875091
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This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that Designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.
標(biāo)簽：
Integrated
Digital
Circuit
Design
上傳時(shí)間：
2013-11-04
上傳用戶(hù)：life840315
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Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.
標(biāo)簽：
數(shù)字接收器
信號(hào)鏈
噪聲分析
上傳時(shí)間：
2014-12-05
上傳用戶(hù)：cylnpy
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Most circuit Designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator clockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased clock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At clock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
標(biāo)簽：
二極管
導(dǎo)通
開(kāi)關(guān)穩(wěn)壓器
上傳時(shí)間：
2013-10-10
上傳用戶(hù)：誰(shuí)偷了我的麥兜
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Radio Frequency Integrated Circuit Design
I enjoyed reading this book for a number of reasons. One reason is that itaddresses high-speed analog design in the context of microwave issues. This isan advanced-level book, which should follow courses in basic circuits andtransmission lines. Most analog integrated circuit Designers in the past workedon applications at low enough frequency that microwave issues did not arise.As a consequence, they were adept at lumped parameter circuits and often notcomfortable with circuits where waves travel in space. However, in order todesign radio frequency (RF) communications integrated circuits (IC) in thegigahertz range, one must deal with transmission lines at chip interfaces andwhere interconnections on chip are far apart. Also, impedance matching isaddressed, which is a topic that arises most often in microwave circuits. In mycareer, there has been a gap in comprehension between analog low-frequencyDesigners and microwave Designers. Often, similar issues were dealt with in twodifferent languages. Although this book is more firmly based in lumped-elementanalog circuit design, it is nice to see that microwave knowledge is brought inwhere necessary.Too many analog circuit books in the past have concentrated first on thecircuit side rather than on basic theory behind their application in communications.The circuits usually used have evolved through experience, without asatisfying intellectual theme in describing them. Why a given circuit works bestcan be subtle, and often these circuits are chosen only through experience. Forthis reason, I am happy that the book begins first with topics that require anintellectual approach—noise, linearity and filtering, and technology issues. Iam particularly happy with how linearity is introduced (power series). In therest of the book it is then shown, with specific circuits and numerical examples,how linearity and noise issues arise.
標(biāo)簽：
Rogers
Radio
John
Freq
上傳時(shí)間：
2014-12-23
上傳用戶(hù)：han_zh
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The Circuit Designer’s Companion Second edition Tim Williams
標(biāo)簽：
Designers
Companion
Circuit
PCB
上傳時(shí)間：
2013-11-04
上傳用戶(hù)：fredguo
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This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, Designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標(biāo)簽：
pci
PCB
設(shè)計(jì)規(guī)范
上傳時(shí)間：
2013-10-15
上傳用戶(hù)：busterman
