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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you
solely for use in the development of Designs to operate with Xilinx hardware devices. You may not reproduce,
distribute, republish, download, display, post, or transmit the Documentation in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.
Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx
assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections
or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be
provided to you in connection with the Information.
標(biāo)簽：
CPLD
上傳時(shí)間：
2013-10-22
上傳用戶：李哈哈哈
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We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, Designs would never needto be changed because of design errors, but we allknow that sometimes this is necessary.
標(biāo)簽：
276
WP
可編程
測(cè)試
上傳時(shí)間：
2013-11-04
上傳用戶：leixinzhuo
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This is the Xilinx Dual Processor Reference Designs suite. The Designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The Designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference Designs that show various forms of interaction between the two processors.
標(biāo)簽：
XAPP
996
雙處理器
參考設(shè)計(jì)
上傳時(shí)間：
2013-10-29
上傳用戶：旭521
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The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA Designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
標(biāo)簽：
VxWorks
403
ML
嵌入式
上傳時(shí)間：
2013-10-26
上傳用戶：agent
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This white paper discusses how market trends, the need for increased productivity, and new legislation have
accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is
changing the paradigms of safety Designs and will greatly reduce development effort, system complexity, and time to
market. This allows FPGA users to design their own customized safety controllers and provides a significant
competitive advantage over traditional microcontroller or ASIC-based Designs.
Introduction
The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in
cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas
around machines such as fast-moving robots, and distributed control systems in process automation equipment such
as those used in petrochemical plants.
The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of
electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing
safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was
developed in the mid-1980s and has been revised several times to cover the technical advances in various industries.
In addition, derivative standards have been developed for specific markets and applications that prescribe the
particular requirements on functional safety systems in these industry applications. Example applications include
process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC
62304), automotive (ISO 26262), power generation, distribution, and transportation.
圖Figure 1. Local Safety System
標(biāo)簽：
FPGA
安全系統(tǒng)
上傳時(shí)間：
2013-11-14
上傳用戶：zoudejile
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怎樣使用Nios II處理器來(lái)構(gòu)建多處理器系統(tǒng)
Chapter 1. Creating Multiprocessor Nios II Systems
Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1
Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2
Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3
Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3
Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4
Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4
Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8
Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Software Design Considerations for Multiple Processors . . .. . . . . 1–9
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13
Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15
Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15
Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16
Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17
Getting Started with the multiprocessor_tutorial_start Design Example 1–17
Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19
Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22
Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27
Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
標(biāo)簽：
Nios
處理器
多處理器
上傳時(shí)間：
2013-11-21
上傳用戶：lo25643
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Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference Designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽：
Base-Station
Applications
Single-Chip
Transceiver
上傳時(shí)間：
2013-11-05
上傳用戶：超凡大師
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In the past decade, the size and complexity of manyFPGA Designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's Designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
標(biāo)簽：
AXI4
379
wp
即插即用
上傳時(shí)間：
2013-11-11
上傳用戶：csgcd001
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This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing Designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
標(biāo)簽：
XAPP
JTAG
424
ACE
上傳時(shí)間：
2013-10-22
上傳用戶：gai928943
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This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA Designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽：
Spartan
XAPP
FPGA
098
上傳時(shí)間：
2013-11-01
上傳用戶：wojiaohs
