Realization of alogrithm of chaos detection by Determining Lyapunov exponents.
標(biāo)簽： Realization Determining alogrithm detection
上傳時(shí)間： 2013-12-25
上傳用戶：R50974
Determining embedding dimension for phase-space reconstruction using a geometrical construction. It is very important reference for time forecast in chaos sequence.
標(biāo)簽： reconstruction construction Determining phase-space
上傳時(shí)間： 2013-12-23
上傳用戶：weiwolkt
This chapter contains sample programs for Determining capacity. The reader is advised to go through the coding. The file "capacity_water.m" is for measuring the waterfilling capacity. It should be made to work with a file similar to "capacity_plot_main.m". The latter file deals with all the other capacity plots given in the book in Chapter 2. All programs are verified with MATLAB versions 6.0 and above with signal processing and communications toolboxes.
標(biāo)簽： Determining capacity contains programs
上傳時(shí)間： 2016-08-24
上傳用戶：yph853211
Useful guidelines that aid in Determining when to stop testing a given software product.
標(biāo)簽： Determining guidelines software product
上傳時(shí)間： 2013-11-25
上傳用戶：我干你啊
a file for Determining a polynomial degrees
標(biāo)簽： Determining polynomial degrees file
上傳時(shí)間： 2013-12-16
上傳用戶：xuan‘nian
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof Determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2013-10-16
上傳用戶：牛布牛
This application note describes how to build a system that can be used for Determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時(shí)間： 2013-10-15
上傳用戶：euroford
This application note describes how to build a system that can be used for Determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時(shí)間： 2014-11-26
上傳用戶：erkuizhang
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof Determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2014-03-03
上傳用戶：zhtzht
假近鄰法(False Nearest Neighbor, FNN)計(jì)算嵌入維的Matlab程序 文件夾說(shuō)明： Main_FNN.m - 程序主函數(shù)，直接運(yùn)行此文件即可 LorenzData.dll - 產(chǎn)生Lorenz時(shí)間序列 PhaSpaRecon.m - 相空間重構(gòu) fnn_luzhenbo.dll - 假近鄰計(jì)算主函數(shù) SearchNN.dll - 近鄰點(diǎn)搜索 buffer_SearchNN_1.dll - 近鄰點(diǎn)搜索緩存1 buffer_SearchNN_2.dll - 近鄰點(diǎn)搜索緩存2 參考文獻(xiàn)： M.B.Kennel, R.Brown, H.D.I.Abarbanel. Determining embedding dimension for phase-space reconstruction using a geometrical construction[J]. Phys. Rev. A 1992,45:3403.
標(biāo)簽： Main_FNN Neighbor Nearest Matlab
上傳時(shí)間： 2013-12-10
上傳用戶：songnanhua
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