Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計(jì)與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The DevelopMent of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:
標(biāo)簽： S參數(shù)
上傳時(shí)間： 2013-12-19
上傳用戶：aa54
提出了一種以ARM微處理器為控制核心的遠(yuǎn)程無(wú)線視頻監(jiān)控終端的設(shè)計(jì)方案，其監(jiān)控終端的硬件設(shè)計(jì)包括視頻采集處理、中央管理控制、無(wú)線傳輸3個(gè)模塊。并給出了監(jiān)控終端的軟件開(kāi)發(fā)平臺(tái)和開(kāi)發(fā)模式的系統(tǒng)啟動(dòng)代碼、嵌入式Linux系統(tǒng)移植以及驅(qū)動(dòng)程序和應(yīng)用程序。測(cè)試結(jié)果表明，該監(jiān)控終端設(shè)計(jì)方案合理、有效，基本滿足監(jiān)控需求。 Abstract: A remote wireless video monitoring terminal design， which uses ARM microprocessor as its core control， is proposed in this paper.The hardware design of monitoring terminal system is composed of the video acquisition and processing module， the central management and control module， wireless transmission module.Meanwhile the monitoring terminal-s software DevelopMent platform and DevelopMent patterns are designed. Also the design of the system-s start codes， embedded Linux system-s transplantation process， driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable， effective， basically meet monitoring requirements.
標(biāo)簽： ARM 遠(yuǎn)程無(wú)線 視頻監(jiān)控 終端設(shè)計(jì)
上傳時(shí)間： 2013-11-13
上傳用戶：wanqunsheng
解壓包包含了C語(yǔ)言入門(mén)經(jīng)典教程和Visuak c++軟件 【基本簡(jiǎn)介】 Visual C++是一個(gè)功能強(qiáng)大的可視化軟件開(kāi)發(fā)工具。自1993年Microsoft公司推出Visual C++1.0后，隨著其新版本的不斷問(wèn)世，Visual C++已成為專業(yè)程序員進(jìn)行軟件開(kāi)發(fā)的首選工具。 雖然微軟公司推出了Visual C++.NET(Visual C++7.0)，但它的應(yīng)用的很大的局限性，只適用于Windows 2000,Windows XP和Windows NT4.0。所以實(shí)際中，更多的是以Visual C++6.0為平臺(tái)。 Visual C++6.0不僅是一個(gè)C++編譯器，而且是一個(gè)基于Windows操作系統(tǒng)的可視化集成開(kāi)發(fā)環(huán)境（integrated DevelopMent environment,IDE）。Visual C++6.0由許多組件組成，包括編輯器、調(diào)試器以及程序向?qū)ppWizard、類向?qū)lass Wizard等開(kāi)發(fā)工具。 這些組件通過(guò)一個(gè)名為Developer Studio的組件集成為和諧的開(kāi)發(fā)環(huán)境。 在Visual C++ 6.0 企業(yè)版的基礎(chǔ)上集成官方的SP6升級(jí)補(bǔ)丁制作而成！免序列號(hào)，安裝完即可使用，無(wú)需再打補(bǔ)丁！ 【使用方法】 有些朋友反應(yīng)在安裝后出現(xiàn) "Error spawning error" 可以看看下面綠色軟件找到的一些解決方案： 點(diǎn)擊VC“TOOLS（工具）”—>“Option（選擇）”—>“Directories（目錄）”重新設(shè)置“Excutable Fils、Include Files、Library Files、Source Files”的路徑。很多情況可能就一個(gè)盤(pán)符的不同（例如你的VC裝在C，但是這些路徑全部在D），改過(guò)來(lái)就OK了。
標(biāo)簽： C語(yǔ)言 程序設(shè)計(jì) 軟件
上傳時(shí)間： 2013-10-09
上傳用戶：hui626493
Ultiboard PCB introduction
標(biāo)簽： DevelopMent ultiboard PCB
上傳時(shí)間： 2013-10-09
上傳用戶：yl1140vista
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce DevelopMent effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-14
上傳用戶：zoudejile
Nios II軟件構(gòu)建工具入門(mén) The Nios® II Software Build Tools (SBT) allows you to construct a wide variety of complex embedded software systems using a command-line interface. From this interface, you can execute Software Built Tools command utilities, and use scripts other tools) to combine the command utilities in many useful ways. This chapter introduces you to project creation with the SBT at the command line This chapter includes the following sections: ■ “Advantages of Command-Line Software DevelopMent” ■ “Outline of the Nios II SBT Command-Line Interface” ■ “Getting Started in the SBT Command Line” ■ “Software Build Tools Scripting Basics” on page 3–8
上傳時(shí)間： 2013-11-15
上傳用戶：nanxia
面向Eclips的Nios II軟件構(gòu)建工具手冊(cè) The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ DevelopMent toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent DevelopMent platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software DevelopMent tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時(shí)間： 2013-11-02
上傳用戶：瓦力瓦力hong
Abstract: This application note discusses the DevelopMent and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時(shí)間： 2013-11-05
上傳用戶：超凡大師
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start DevelopMent simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-10-09
上傳用戶：evil
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the DevelopMent of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the DevelopMent of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2013-11-20
上傳用戶：pzw421125
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