implemention of FPGA and DSP linking port, using Asynchronous mode
標簽： implemention Asynchronous linking using
上傳時間： 2013-08-22
上傳用戶：fhjdliu
Cadence Verilog Language and Simulation
標簽： Simulation Language Cadence Verilog
上傳時間： 2013-09-06
上傳用戶：yl1140vista
cadence material includes caden_layout,CADENCE_20Manual,cs5710-layout1x2 and manual
上傳時間： 2013-09-10
上傳用戶：kao21
Can convert data file(txt format)to CAD(scr)file,and draw curve!
上傳時間： 2013-09-11
上傳用戶：天空說我在
proteus and keil 兩者聯合實現Max7221動態顯示，解決一些初學者對proteus and keil如何實現的困惑；
上傳時間： 2013-09-24
上傳用戶：zsjzc
How we make connection with Proteus and the LCD, (project included)
標簽： connection Proteus make with
上傳時間： 2013-09-24
上傳用戶：lihairui42
keil and proteus聯合演示顯示效果，可實現音樂的播放，對初學者比較有用；很好的例子
上傳時間： 2013-09-25
上傳用戶：yangqian
the practice of proteus and avr
上傳時間： 2013-09-29
上傳用戶：tom_man2008
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator clockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased clock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At clock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
上傳時間： 2013-10-10
上傳用戶：誰偷了我的麥兜
Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
標簽： Considerations Guidelines and Design
上傳時間： 2013-10-14
上傳用戶：ysystc699
