This program accesses a SPI EEPROM using polled mode access. The F12x MCU is configured in 4-wire Single Master Mode, and the EEPROM is the only slave device connected to the SPI bus. The read/write operations are tailored to access a Microchip 4 kB EEPROM
標(biāo)簽： configured accesses program EEPROM
上傳時(shí)間： 2016-03-29
上傳用戶：gut1234567
The jacobi.f program solves the Helmholtz equation on a regular mesh, using an iterative Jacobi method with over-relaxation. Parallelism is exploited in both the solver and the numerical error checking
標(biāo)簽： Helmholtz iterative equation program
上傳時(shí)間： 2016-04-03
上傳用戶：杜瑩12345
模式識別學(xué)習(xí)綜述.該論文的英文參考文獻(xiàn)為303篇.很有可讀價(jià)值.Abstract— Classical and recent results in statistical pattern recognition and learning theory are reviewed in a two-class pattern classification setting. This basic model best illustrates intuition and analysis techniques while still containing the essential features and serving as a prototype for many applications. Topics discussed include nearest neighbor, kernel, and histogram methods, Vapnik–Chervonenkis theory, and neural networks. The presentation and the large (thogh nonexhaustive) list of references is geared to provide a useful overview of this field for both specialists and nonspecialists.
標(biāo)簽： statistical Classical Abstract pattern
上傳時(shí)間： 2013-11-25
上傳用戶：www240697738
The program implements three large-margin thresholded ensemble algorithms for ordinal regression. It includes an improved RankBoost algorithm, the ORBoost-LR algorithm, and the ORBoost-All algorithm.
標(biāo)簽： large-margin thresholded implements algorithms
上傳時(shí)間： 2014-10-28
上傳用戶：zhichenglu
The IA-32 Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference (Order Number 245471) is part of a three-volume set that describes the architecture and programming environment of all IA-32 Intel® Architecture processors. the IA-32 Intel Architecture Software Developer’s Manual, Volume 2, describes the instructions set of the processor and the opcode structure. These two volumes are aimed at application programmers who are writing programs to run under existing operating systems or executives.
標(biāo)簽： Architecture Instruction Developer Reference
上傳時(shí)間： 2013-12-15
上傳用戶：xsnjzljj
CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
標(biāo)簽： specification the designed diagrams
上傳時(shí)間： 2013-12-27
上傳用戶：yyyyyyyyyy
A digital fi‘equeney meter designed with FPGA development software Q-~us 11 is introduced．The 1 Hz—l MHz input measured pulse signals of the digital ii‘equency meter can be used for measuring frequency，period，pulse width and duty ratio，etc．The test results stably display O71 3 seven—segment numeric tubes，and the measuring ranges may be switched over automatically．The measuring error is equal to or less than 0．1％．
標(biāo)簽： development introduced designed software
上傳時(shí)間： 2016-04-09
上傳用戶：stewart·
// This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
標(biāo)簽： configured accesses program EEPROM
上傳時(shí)間： 2014-01-18
上傳用戶：liglechongchong
// This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
標(biāo)簽： configured accesses program EEPROM
上傳時(shí)間： 2016-04-12
上傳用戶：qb1993225
This will sample all 8 A/D-channels by the continous mode. Each end of conversion will call an interrupt routine, where the AD-channel is put to Port4[2..0] and the upper nibble of the result is put to Port4[7..4]. Port 4 is connected to the user LEDs of the FlashCan100P Evaluation-Board
標(biāo)簽： will D-channels conversion continous
上傳時(shí)間： 2013-12-09
上傳用戶：zm7516678
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