AT91SAM9261EK CE5.0 Binary EValuation v1.7.0
標(biāo)簽： EValuation Binary 9261 5.0
上傳時間： 2013-12-21
上傳用戶：410805624
IAR Embedded Workbench for 8051 8.10 EValuation的license破解，成功安裝
標(biāo)簽： license 8051 8.10 IAR
上傳時間： 2013-04-24
上傳用戶：變形金剛
Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures， follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training EValuation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process， it can not only be used in teaching， but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.
標(biāo)簽： 電臺維修 模擬訓(xùn)練 方法研究 系統(tǒng)設(shè)計
上傳時間： 2013-11-19
上傳用戶：3294322651
本書分三部分介紹在美國廣泛應(yīng)用的、高功能的M68HC11系列單片機(jī)(8位機(jī) ，Motorola公司)。內(nèi)容包括Ｍ６８HC１１的結(jié)構(gòu)與其基本原理、開發(fā)工具EVB(性能評估板)以及開發(fā)和應(yīng)用技術(shù)。本書在介紹單片機(jī)硬、軟件的基礎(chǔ)上，進(jìn)一步介紹了在美國實驗室內(nèi)，如何應(yīng)用PC機(jī)及EVB來進(jìn)行開發(fā)工作。通過本書的介紹，讀者可了解這種單片機(jī)的原理并學(xué)會開發(fā)和應(yīng)用方法。本書可作為大專院校單片機(jī)及其實驗的教材(本科、短訓(xùn)班)。亦可供開發(fā)、應(yīng)用單片機(jī)的各專業(yè)(計算機(jī)、機(jī)電、化工、紡織、冶金、自控、航空、航海……)有關(guān)技術(shù)人員參考。 第一部分 M68HC11 結(jié)構(gòu)與原理Motorola單片機(jī) 1 Motorla單片機(jī) 1.1 概述 1.1.1 Motorola 單片機(jī)發(fā)展概況(3) 1.1.2 Motorola 單片機(jī)結(jié)構(gòu)特點(4) 1.2 M68HC11系列單片機(jī)(5) 1.2.1 M68HC11產(chǎn)品系列(５) 1.2.2 MC68HC11E9特性(６) 1.2.3 MC68HC11E9單片機(jī)引腳說明(８) 1.3 Motorola 32位單片機(jī)(１４) 1.3.1中央處理器(CPU32)(１５) 1.3.2 定時處理器(TPU)(１６) 1.3.3 串行隊列模塊(QSM)(１６) 1.3.4 系統(tǒng)集成模塊 (SIM)(１６) 1.3.5 RAM(１７) 2 系統(tǒng)配置與工作方式 2.1 系統(tǒng)配置(１９) 2.1.1 配置寄存器CONFIG(１９) 2.1.2 CONFIG寄存器的編程與擦除(２０) 2?2 工作方式選擇(２１) 2.3 M68HC11的工作方式(２３) 2.3.1 普通單片工作方式(２３) 2.3.2 普通擴(kuò)展工作方式(２３) 2.3.3 特殊自舉方式(２７) 2.3.4 特殊測試方式(２８) 3 中央處理器(CPU)與片上存儲器 3.1 CPU寄存器(３１) 3?1?1 累加器A、B和雙累加器D(３２) 3.1.2 變址寄存器X、Y(３２) 3.1.3 棧指針SP(３２) 3.1.4 程序計數(shù)器PC(３３) 3.1.5 條件碼寄存器CCR(３３) 3.2 片上存儲器(３４) 3.2.1 存儲器分布(３４) 3.2.2 RAM和INIT寄存器(３５) 3.2.3 ROM(３７) 3.2.4 EEPROM(３７) 3.3 M68HC11 CPU的低功耗方式(３９) 3.3.1 WAIT方式(３９) 3.3.2 ＳＴＯP方式(４０) 4 復(fù)位和中斷 4.1 復(fù)位(４１) 4.1.1 M68HC11的系統(tǒng)初始化條件(４１) 4.1.2 復(fù)位形式(４３) 4.2 中斷(４８) 4.2.1 條件碼寄存器CCR中的中斷屏蔽位(４８) 4.2.2 中斷優(yōu)先級與中斷矢量(４９) 4.2.3 非屏蔽中斷(５２) 4.2.4 實時中斷(５３) 4.2.5 中斷處理過程(５６) 5 M68HC11指令系統(tǒng) 5.1 M68HC11尋址方式(５９) 5.1.1 立即尋址(IMM)(５９) 5.1.2 擴(kuò)展尋址(EXT)(６０) 5.1.3 直接尋址(DIR)(６０) 5.1.4 變址尋址(INDX、INDY)(６１) 5.1.5 固有尋址(INH)(６２) 5.1.6 相對尋址(REL)(６２) 5.1.7 前置字節(jié)(６３) 5.2 M68HC11指令系統(tǒng)(６３) 5.2.1 累加器和存儲器指令(６３) 5.2.2 棧和變址寄存器指令(６８) 5.2.3 條件碼寄存器指令(６９) 5.2.4 程序控制指令(７０) 6 輸入與輸出 6.1 概述(７３) 6.2 并行I／O口(７４) 6.2.1 并行I／O寄存器(７４) 6.2.2 應(yīng)答I／O子系統(tǒng)(７６) 6?3 串行通信接口SCI(８２) 6.3.1 基本特性(８３) 6.3.2 數(shù)據(jù)格式(８３) 6.3.3 SCI硬件結(jié)構(gòu)(８４) 6.3.4 SCI寄存器(８６) 6.4 串行外圍接口SPI(９２) 6.4.1 SPI特性(９２) 6.4.2 SPI引腳信號(９２) 6.4.3 SPI結(jié)構(gòu)(９３) 6.4.4 SPI寄存器(９５) 6.4.5 SPI系統(tǒng)與外部設(shè)備進(jìn)行串行數(shù)據(jù)傳輸(９９) 7 定時器系統(tǒng)與脈沖累加器 7.1 概述(１０５) 7.2 循環(huán)計數(shù)器(１０７) 7.2.1 時鐘分頻器(１０７) 7.2.2 計算機(jī)正常工作監(jiān)視功能(１１０) 7.2.3 定時器標(biāo)志的清除(１１０) 7.3 輸入捕捉功能(１１１) 7.3.1 概述(１１１) 7.3.2 定時器輸入捕捉鎖存器(TIC1、TIC2、TIC3) 7.3.3 輸入信號沿檢測邏輯(１１３) 7.3.4 輸入捕捉中斷(１１３) 7.4 輸出比較功能(１１４) 7.4.1 概述(１１４) 7.4.2 輸出比較功能使用的寄存器(１１６) 7.4.3 輸出比較示例(１１８) 7.5 脈沖累加器(１１９) 7.5.1 概述(１１９) 7.5.2 脈沖累加器控制和狀態(tài)寄存器(１２１) 8 A／Ｄ轉(zhuǎn)換系統(tǒng) 8.1 電荷重新分布技術(shù)與逐次逼近算法(１２５) 8.1.1 基本電路(１２５) 8.1.2 A／D轉(zhuǎn)換逐次逼近算法原理(１３０) 8.2 M68HC11中Ａ／Ｄ轉(zhuǎn)換的實現(xiàn)方法(１３１) 8.2.1 逐次逼近Ａ／Ｄ轉(zhuǎn)換器(１３１) 8.2.2 控制寄存器(１３２) 8.2.3 系統(tǒng)控制邏輯(１３５)? 9 單片機(jī)的內(nèi)部操作 9.1 用立即> 圖書前言 美國Motorola公司從80年代中期開始推出的M68HC11系列單片機(jī)是當(dāng)今功能最強、性能／價格比最好的八位單片微計算機(jī)之一。在美國，它已被廣泛地應(yīng)用于教學(xué)和各種工業(yè)控制系統(tǒng)中。? 該單片機(jī)有豐富的I／O功能，完善的系統(tǒng)保護(hù)功能和軟件控制的節(jié)電工作方式 。它的指令系統(tǒng)與早期Motorola單片機(jī)MC6801等兼容，同時增加了91條新指令。其中包含16位乘法、除法運算指令等。 為便于用戶開發(fā)和應(yīng)用M68HC11單片機(jī)，Motorola公司提供了多種開發(fā)工具。M68HC11 EVB (EValuation Board)性能評估板就是一種M68HC11系列單片機(jī)的廉價開發(fā)工具。它既可用來 調(diào)試用戶程序，又可在仿真方式下運行。為方便用戶，M68HC11 EVB可與IBM?PC連接 ，借助于交叉匯編、通信程序等軟件，在IBM?PC上調(diào)試程序。? 本書分三部分(共15章)介紹了M68HC11的結(jié)構(gòu)和基本原理、開發(fā)工具-EVB及開發(fā)應(yīng)用實例等。第一部分（１～９章），介紹M68HC11的結(jié)構(gòu)和基本原理。包括概述，系統(tǒng)配置與工作方式、CPU和存儲器、復(fù)位和中斷、指令系統(tǒng)、I／Ｏ、定時器系統(tǒng)和脈沖累加器、Ａ／Ｄ轉(zhuǎn)換系統(tǒng)、單片機(jī)的內(nèi)部操作等。第二部分(１０～１１章)，介紹M68HC11 EVB的原理和技術(shù)特性以及EVB的應(yīng)用。第三部分(１２～１５章)，介紹M68HC11的開發(fā)與應(yīng)用技術(shù)。包括基本的編程練習(xí)、應(yīng)用程序設(shè)計、接口實驗、接口設(shè)計及應(yīng)用等。 讀者通過學(xué)習(xí)本書，不僅可了解M68HC11的硬件、軟件，而且可了解使用EVB開發(fā)和應(yīng)用M68HC11單片機(jī)的方法。在本書的第三部分專門提供了一部分實驗和應(yīng)用程序。? 本書系作者張寧作為高級訪問學(xué)者，應(yīng)邀在美國馬薩諸塞州洛厄爾大學(xué)(University of Massachusetts Lowell)工作期間完成的。全書由張寧執(zhí)筆。在編著過程中，美國洛厄爾大學(xué)的R·代克曼教授?(Professor Robert J. Dirkman)多次與張寧一起討論、研究，并提供部分資料及實驗數(shù)據(jù)。參加編寫和審校等工作的還有王云霞、孫曉芳、劉安魯、張籍、來安德、張楊等同志。? 為將M68HC11系列單片機(jī)盡快介紹給我國，美國Motorola公司的Terrence M.S.Heng先生曾大力支持本書的編著和出版。在此表示衷心感謝。
上傳時間： 2013-10-27
上傳用戶：rlgl123
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive EValuation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. EValuation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. EValuation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive EValuation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D EValuation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時間： 2013-11-14
上傳用戶：fdmpy
Stellaris LM3S8962 以太網(wǎng) +CAN 評估套件 (Stellaris LM3S8962 EValuation Kit for Ethernet and CAN) 可為采用Stellaris 微處理器啟動以太網(wǎng)及控制器局域網(wǎng) (CAN) 的應(yīng)用設(shè)計提供一種低成本途徑。LM3S8962 評估板 (EVB) 既可作為完整的評估目標(biāo)，也可以作為能夠連接至任何客戶目標(biāo)板上 Stellaris 器件的調(diào)試工具。僅需使用配套提供的 USB 線纜即可通過 PC 主機(jī)為評估板提供電源并實現(xiàn)通信傳輸。
標(biāo)簽： Stellaris S8962 8962 LM3
上傳時間： 2013-12-21
上傳用戶：semi1981
The Maxim Integrated 71M6541-DB REV 3.0 Demo Board is a demonstration board for evaluating the 71M6541 device for single-phase electronic energy metering applications in conjunction with the Remote Sensor Inter-face. It incorporates a 71M6541 integrated circuit, a 71M6601 Remote Interface IC, peripheral circuitry such as a serial EEPROM, emulator port, and on-board power supply. A serial to USB converter allows communication to a PC through a USB port. The Demo Board allows the EValuation of the 71M6541 energy meter chip for measurement accuracy and overall system use.
上傳時間： 2013-11-06
上傳用戶：雨出驚人love
STM32學(xué)習(xí)資料
標(biāo)簽： EValuation 320518 Board EVAL
上傳時間： 2013-10-31
上傳用戶：看到了沒有
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