This book is intended for "hands-on" developers or advanced students interested in understanding the strategies and tactics of concurrent network programming using C++ and object-oriented design. We describe the key design dimensions, patterns, and principles needed to develop flexible and efficient concurrent networked applications quickly and easily. Our numerous C++ code EXAMples reinforce the design concepts and illustrate concretely how to use the core classes in ACE right away. We also take you "behind the scenes" to understand how and why the IPC and concurrency mechanisms in the ACE toolkit are designed the way they are. This material will help to enhance your design skills and to apply C++ and patterns more effectively in your own object-oriented networked applications.
Name:neural Network Control, for Matlab,tipical description for control problems with NN method, additionally, there are some useful EXAMples to be referenced.
英文版,pdf格式。
詳細說明：
Title: STL Tutorial and Reference Guide: C++ Programming with the Standard Template Library (2nd Edition)
URL: http://www.amazon.com/exec/obidos/tg/detail/-/0201379236/
ISBN: 0201379236
Author: David R. Musser / Gillmer J. Derge / Atul Saini / Gilmer J. Derge
Publisher: Addison-Wesley
Page: 560
Edition: 2nd edition (March 27, 2001)
Catalog: C++
Format: PDF
Size: 3.8M
Supplier: December
Summary: The Standard Template Library was created as the first library of genetic algorithms and data structures, with four ideas in mind: generic programming, abstractness without loss of efficiency, the Von Neumann computation model, and value semantics. This guide provides a tutorial, a description of each element of the library, and sample applications. The expanded second edition includes new code EXAMples and demonstrations of the use of STL in real-world C++ software development it reflects changes made to STL for the final ANSI/ISO C++ language standard.
Over the years, this bestselling guide has helped countless programmers learn how to support computer peripherals under the Linux operating system, and how to develop new hardware under Linux. Now, with this third edition, it s even more helpful, covering all the significant changes to Version 2.6 of the Linux kernel. Includes full-featured EXAMples that programmers can compile and run without special hardware.
This m-file simulates MPSK (theoretical and simulated) with Gray coding
This m-file simulates MPSK (BPSK,QPSK,8PSK)with theoretical and simulated results using Gray coding. Numerical EXAMples of a satellite link design are shown using QPSK and/or 8PSK when the bit rate(Rb)is greater than the channel bandwidth Wc (Band-limited channel).
Problem Statement
You are given a string input. You are to find the longest substring of input such that the reversal of the substring is also a substring of input. In case of a tie, return the string that occurs earliest in input.
Definition
Class: ReverseSubstring
Method: findReversed
Parameters: string
Returns: string
Method signature: string findReversed(string input)
(be sure your method is public)
Notes
The substring and its reversal may overlap partially or completely.
The entire original string is itself a valid substring (see example 4).
Constraints
input will contain between 1 and 50 characters, inclusive.
Each character of input will be an uppercase letter ( A - Z ).
EXAMples
0)
"XBCDEFYWFEDCBZ"
Returns: "BCDEF"
We see that the reverse of BCDEF is FEDCB, which appears later in the string.
1)
Verilog and VHDL狀態機設計，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world EXAMples.
This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP EXAMples directory.
