With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow of bandwidth-limited speech processing. Today, the main appli- cations of audio DSP are high quality audio coding and the digital generation and manipulation of music signals. They share common research topics including percep- tual measurement techniques and analysis/synthesis methods. Smaller but nonetheless very important topics are hearing aids using signal processing technology and hardware architectures for digital signal processing of audio. In all these areas the last decade has seen a significant amount of application oriented research.
A passive optical network (PON) is a point-to-multipoint, fiber to the premises network architecture in which unpowered optical splitters are used to enable a single optical fiber to serve multiple premises, typically 32-128. A PON consists of an Optical Line Termination (OLT) at the service provider s central office and a number of Optical Network Units (ONUs) near end users. A PON configuration reduces the amount of fiber and central office equipment required compared with point to point architectures
Sensing and planning are at the core of robot motion. Traditionally,
mobile robots have been used for performing various tasks
with a general-purpose processor on-board. This book grew out of
our research enquiry into alternate architectures for sensor-based
robot motion. It describes our research starting early 2002 with the
objectives of obtaining a time, space and energy-efficient solution
for processing sensor data for various robotic tasks.
New algorithms and architectures have been developed for
exploration and other aspects of robot motion. The research has
also resulted in design and fabrication of an FPGA-based mobile
robot equipped with ultrasonic sensors. Numerous experiments
with the FPGA-based mobile robot have also been performed and
they confirm the efficacy of the alternate architecture.
VHDL implementation of the twofish cipher for 128,192 and 256 bit keys.
The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.
