It is an experimental testing for python M2Crypto module. M2Crypto is not well document. User may not know how to use SHA256 when signing and verify with RSA. It also have not enough document to show how to use DES to encrypt and decrypt. Here also includes source codes for performance Evaluation of the algorithms. This experimental program explore all this issue and may be helpful for some one who using python for doing encryption with RSA and DES.
This application report presents basic code for initializing and operating the TMS320LF240x DSP devices. Two functionally equivalent example progra ms are presented: one written in assembly language and the other in C language. Detailed discussions of each program are provided that explain numerous compiler and assembler directives, code requirements, and hardware-related requirements. The programs are ready to run on either the TMS320LF2407 Evaluation Module (EVM) or the eZdsp LF2407 development kit. However, they are also intended for use as a code template for any TMS320LF240x (LF240x) or TMS320LF240xA (LF240xA) DSP target system.
This sample displays a basic integer calculator powered
by the 8051 microcontroller. Although Keil C51 has a
full floating point math library the Evaluation version
is restricted to 2k of object code, so we have constrained
this sample to integer maths in order to fit within this limit.
The program for this design was written in C using the
Keil uVision 2 IDE for which Proteus VSM provides
a Debug Monitor driver.
Instructions for configuring Proteus to run in conjunction
with the Keil environment can be found by editing the
8051 microcontroller on the schematic (point at it and
press CTRL-E) and then clicking on the help button
on the Edit Component dialogue form.
DESCRIPTION
===========
This example project shows how to use the IAR Embedded Workbench for ARM
to develop code for the Atmel AT91SAM9261 Evaluation boards.
It shows basic use of parallel I/O, timer and the interrupt controller.
It starts by showing different patterns on the LED s separated by half second.
COMPATIBILITY
=============
The project is compatible with the AT91SAM9261-EK board.
state of art language modeling methods:
An Empirical Study of Smoothing Techniques for Language Modeling.pdf
BLEU, a Method for Automatic Evaluation of Machine Translation.pdf
Class-based n-gram models of natural language.pdf
Distributed Language Modeling for N-best List Re-ranking.pdf
Distributed Word Clustering for Large Scale Class-Based Language Modeling in.pdf
多項式擬合的MATLAB工具。只要具有以下幾個函數
POLYFITN - A general n-dimensional polynomial fitting tool
POLYVALN - An Evaluation tool for polynomials produced by polyfitn
POLYN2SYMPOLY - A conversion tool to generate a sympoly from the results of polyfitn
POLYN2SYM - A conversion tool to generate a symbolic toolbox object from the results of polyfitn
This document constitutes the user manual for the YAMON™ ROM monitor.
YAMON (“Yet Another MONitor”) is the ROM monitor used on MIPS Technologies Evaluation and reference boards.
The target audience for this document is users of those boards. This would typically be engineers developing hardware
or software including compilers, RTOS and other tools.
Currently, the following boards/CPUs are supported by YAMON :
• Atlas™ with MIPS32 4K™ or MIPS64 5K™ class of CPUs.
• Atlas with QED RM5261® .
• Malta™ with MIPS32 4K or MIPS64 5K class of CPUs.
• Malta with QED RM5261® .
• SEAD™ with MIPS32 4K or MIPS64 5K class of CPUs.
• SEAD-2™ with MIPS32 4K or MIPS64 5K class of CPUs.
This paper shows the development of a 1024-point
radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance Evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis
applications.
1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis
2. fpga implemention of a median filter
3. fpga implementation of digital filters
4.hardware acceleration of edge detection algorithm on fpgas
5.implementation and Evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages
6. implementing 2D median filter in fpgas
7.視頻圖像處理與分析的網絡資源
