介紹了用單片機C 語言實現無功補償中電容組循環投切的基本原理和算法，并舉例說明。關鍵詞：循環投切;C51;無功補償中圖分類號： TM76 文獻標識碼： BAbstract: This paper introduces the aplication of C51 in the controlling of capacitorsuits cycle powered to be on and off in reactive compensation.it illustrate thefondamental principle and algorithm with Example.Key words: cycle powered to be on and off; C51; reactive compensation 為提高功率因數，往往采用補償電容的方法來實現。而電容器的容量是由實時功率因數與標準值進行比較來決定的，實時功率因數小于標準值時，需投入電容組，實時功率因數大于標準值時，則需切除電容組。投切方式的不合理，會對電容器造成損壞，現有的控制器多采用“順序投切”方式，在這種投切方式下排序在前的電容器組，先投后切；而后面的卻后投先切。這不僅使處于前面的電容組經常處于運行狀態，積累熱量不易散失，影響其使用壽命，而且使后面的投切開關經常動作，同樣減少壽命。合理的投切方式應為“循環投切”。這種投切方式使先投入的運行的電容組先退出，后投的后切除，從而使各組電容及投切開關使用機率均等，降低了電容組的平均運行溫度，減少了投切開關的動作次數，延長了其使用壽命。
上傳時間： 2014-12-27
上傳用戶：hopy
PROTEUS VSM在單片機系統仿真中的應用:：介紹了單片機系統仿真工具PROTEUS VSM 及其在單片機系統仿真中的應用，給出了具體的應用實例，詳細地介紹了PROTEUS VSM 與Keil uVision3的接口方法。關鍵詞：單片機；Keil uVision3；仿真；外圍器件；PROTEUS VSM； Abstract：This paper introduces the simulation tool for M CU system —PROTEUS VSM ， and presents the application ofPROTEUS VSM in MCU system simulation through an applicable Example．The way of interfacing PROTEUS VSM to Keil uVision3is also presented in details．Keywords：MCU ；Keil uVision3；simulation；peripheral devices；PROTEUS VSM ；
上傳時間： 2013-11-16
上傳用戶：chenxichenyue
This application note describes how to decode standard DTMF tones using the minimum number of external discrete components and a PIC. The two Examples use a PIC which has an 8 bit timer and either a comparator or an ADC, although it can be modified for use on a PIC which has only digital I/O. The Appendices have Example code for the 16C662 (with comparator) and 16F877 (using the ADC). As the majority of the Digital Signal Processing is done in software, little is required in the way of external signal conditioning. Software techniques are used to model the individual elements of a DTMF Decoder IC.
上傳時間： 2013-11-21
上傳用戶：zhaoke2005
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for Example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上傳時間： 2013-10-09
上傳用戶：3294322651
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an Example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small Example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
上傳時間： 2013-11-23
上傳用戶：weixiao99
This application note demonstrates how to write an Inter Integrated Circuit bus driver (I2C) for the XA-S3 16-bitMicrocontroller from Philips Semiconductors.Not only the driver software is given. This note also contains a set of (Example) interface routines and a smalldemo application program. All together it offers the user a quick start in writing a complete I2C system applicationwith the PXAS3x.The driver routines support interrupt driven single master transfers. Furthermore, the routines are suitable foruse in conjunction with real time operating systems.
上傳時間： 2013-11-02
上傳用戶：zw380105939
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingExample, demonstrating a bus-master code. Here we show anExample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The Examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上傳時間： 2013-11-19
上傳用戶：shirleyYim
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-05
上傳用戶：維子哥哥
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS Example.
標簽： Implementing LVDS 522 Bus
上傳時間： 2013-11-10
上傳用戶：frank1234
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an Example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes Example design, testbench; and both implementation and simulation scripts
標簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-23
上傳用戶：leyesome
