tr1 byte "Please input the FIRST 64-bit in hex:FIRST - second",0dh,0ah,0
string byte "remener :use enter to tell high 32-bit from low 32-bit",0dh,0ah,0
examp1 byte "eg: 1234ecdf",0dh,0ah,0
examp2 byte " 03ab2543",0dh,0ah,0
This paper presents several low-latency mixed-timing
FIFO (FIRST-in–FIRST-out) interfaces designs that interface systems
on a chip working at different speeds. The connected systems
can be either synchronous or asynchronous. The designs are then
adapted to work between systems with very long interconnect
delays, by migrating a single-clock solution by Carloni et al.
(1999, 2000, and 2001) (for “l(fā)atency-insensitive” protocols) to
mixed-timing domains. The new designs can be made arbitrarily
robust with regard to metastability and interface operating speeds.
Initial simulations for both latency and throughput are promising.
HDOJ 1047
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Input
The FIRST line of the input contains a single integer T (1 <= T <= 20), the number of test cases. Then T cases follow. The FIRST line of each case contains N, and the second line contains N integers giving the time for each people to cross the river. Each case is preceded by a blank line. There won t be more than 1000 people and nobody takes more than 100 seconds to cross.
Output
For each test case, print a line containing the total number of seconds required for all the N people to cross the river.
Sample Input
1
4
1 2 5 10
Sample Output
17
Input
The input contains blocks of 2 lines. The FIRST line contains the number of sticks parts after cutting, there are at most 64 sticks. The second line contains the lengths of those parts separated by the space. The last line of the file contains zero.
Output
The output should contains the smallest possible length of original sticks, one per line.
Sample Input
9
5 2 1 5 2 1 5 2 1
4
1 2 3 4
0
Sample Output
6
5