When I started writing the first edition of RF Power Amplifiers for Wireless Communications,some time back in 1997, it seemed that I was roaming a largely uninhabitedlandscape. For reasons still not clear to me there were few, if any, otherbooks dedicated to the subject of RF power amplifiers. Right at the same time, however,hundreds of engineers were being assigned projects to design PAs for wirelesscommunications products. It was not, therefore, especially difficult to be successfulwith a book that was fortuitously at the right place and the right time.
標簽： Communications Amplifiers Wireless Edition
上傳時間： 2013-11-12
上傳用戶：YYRR
通信物理層仿真，有代碼，包括BPSK,QPSK,MSK,GMSK,擴頻等等，Artech.House_2002_Simulation.and.Software.Radio.for.Mobile.Communications。
標簽： Communications Simulation Software Artech
上傳時間： 2013-11-01
上傳用戶：jhksyghr
for 51 for arm
上傳時間： 2013-10-10
上傳用戶：xiaoyuer
for 51 for arm
上傳時間： 2013-11-14
上傳用戶：huql11633
Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
標簽： Considerations Guidelines and Design
上傳時間： 2013-11-09
上傳用戶：ls530720646
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-23
上傳用戶：我干你啊
本文論述了狀態機的verilog編碼風格,以及不同編碼風格的優缺點，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標簽： Synthesis Machine Coding Styles
上傳時間： 2013-10-12
上傳用戶：sardinescn
LabVIEW+For+ARM+Lee
上傳時間： 2013-10-26
上傳用戶：franktu
NTFS(NT文件系統) for Linux的一個實現源碼
上傳時間： 2015-01-04
上傳用戶：Divine
站長寫的使用OCI開發Oracle程序的通用函數庫for unix
上傳時間： 2015-01-04
上傳用戶：363186
