關(guān)于FPGA流水線設(shè)計(jì)的論文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
標(biāo)簽：
FPGA
流水線
論文
上傳時(shí)間：
2013-09-03
上傳用戶：wl9454
