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FPGA-based

FPGA-based high-order FIR filter design

FPGA-based high-order FIR filter design

標(biāo)簽： FPGA-based high-order filter design

上傳時間： 2013-08-06

上傳用戶：sssnaxie
fpga based jpge 壓縮算法

fpga based jpge 壓縮算法，性能不錯，

標(biāo)簽： based fpga jpge 壓縮算法

上傳時間： 2013-08-14

上傳用戶：a471778
FPGA-based link layer chip S19202 configuration

FPGA-based link layer chip S19202 configuration

標(biāo)簽： configuration FPGA-based S19202 layer

上傳時間： 2013-08-18

上傳用戶：xsnjzljj
一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

標(biāo)簽： CORDIC algorithms computers survey

上傳時間： 2013-08-31

上傳用戶：lliuhhui
On the design of an FPGA-based OFDM modulator for IEEE 802.11a

On the design of an FPGA-based OFDM modulator for IEEE 802.11a

標(biāo)簽： FPGA-based modulator 802.11 design

上傳時間： 2013-09-02

上傳用戶：zjwangyichao
On the design of an FPGA-based OFDM modulator for IEEE 802.11a

On the design of an FPGA-based OFDM modulator for IEEE 802.11a

標(biāo)簽： FPGA-based modulator 802.11 design

上傳時間： 2014-12-01

上傳用戶：redmoons
一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

標(biāo)簽： CORDIC algorithms computers survey

上傳時間： 2015-11-28

上傳用戶：haohaoxuexi
AN FPGA-based IMPLEMENTATION FOR MEDIAN FILTER MEETING THE REAL-TIME　REQUIREMENTS OF AUTOMATED VIS

AN FPGA-based IMPLEMENTATION FOR MEDIAN FILTER MEETING THE REAL-TIME　REQUIREMENTS OF AUTOMATED VISUAL INSPECTION SYSTEMS

標(biāo)簽： IMPLEMENTATION REQUIREMENTS FPGA-based AUTOMATED

上傳時間： 2013-12-13

上傳用戶：litianchu
FPGA-based link layer chip S19202 configuration

FPGA-based link layer chip S19202 configuration

標(biāo)簽： configuration FPGA-based S19202 layer

上傳時間： 2013-12-27

上傳用戶：z1191176801
Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by

Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.

標(biāo)簽： Raggedstone1 development Spartan3 low-cost

上傳時間： 2013-12-02

上傳用戶：lps11188

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FPGA-based

FPGA-based high-order FIR filter design

fpga based jpge 壓縮算法

FPGA-based link layer chip S19202 configuration

一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

On the design of an FPGA-based OFDM modulator for IEEE 802.11a

On the design of an FPGA-based OFDM modulator for IEEE 802.11a

一篇關(guān)于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

AN FPGA-based IMPLEMENTATION FOR MEDIAN FILTER MEETING THE REAL-TIME　REQUIREMENTS OF AUTOMATED VIS

FPGA-based link layer chip S19202 configuration

Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by