This project attempts to implement a Database using B+Tree. The project has developed a DATABASE SYSTEM with lesser memory consumption. Its API includes simple SQL Statements and the output is displayed on the screen. Certain applications for which several features of existing databases like concurrency control, transaction management, security features are not enabled. B+Trees can be used as an index for Factor access to the data. Help facility is provided to know the syntax of SQL Statements.
t transistor has the characteristics of components of the sensor real-time measurement of voltage and current signals through, obtained quality Factor correction circuit for the feedback and the feedback time, IBM used the feedback field effect transistor implementation, in order to achieve quality Factor correction circ
When working with mathematical simulations or engineering problems, it is not unusual to handle curves that contains thousands of points. Usually, displaying all the points is not useful, a number of them will be rendered on the same pixel since the screen precision is finite. Hence, you use a lot of resource for nothing!
This article presents a fast 2D-line approximation algorithm based on the Douglas-Peucker algorithm (see [1]), well-known in the cartography community. It computes a hull, scaled by a tolerance Factor, around the curve by choosing a minimum of key points. This algorithm has several advantages:
這是一個基于Douglas-Peucker算法的二維估值算法。
//
// Histogram Sample
// This sample shows how to use the Sample Grabber filter for video image processing.
// Conceptual background:
// A histogram is just a frequency count of every pixel value in the image.
// There are various well-known mathematical operations that you can perform on an image
// using histograms, to enhance the image, etc.
// Histogram stretch (aka automatic gain control):
// Stretches the image histogram to fill the entire range of values. This is a "point operation,"
// meaning each pixel is scaled to a new value, without examining the neighboring pixels. The
// histogram stretch does not actually require you to calculate the full histogram. The scaling Factor
// is calculated from the minimum and maximum values in the image.
Real-Time Digital Signal Processing
Implementations, Applications, and Experiments with the TMS320C55x
John Wiley & Sons, Inc. 2001
By Sen M. Kuo and Bob H. Lee
4.6.1 Experiment 4A - Twiddle Factor Generation
4.6.2 Experiment 4B - Complex Data Operation
4.6.3 IExperiment 4C - mplementation of DFT
4.6.4 Experiment 4D - Experiment Using Assembly Routines
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a Factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
The double-density DWT is an improvement upon the critically sampled DWT with important additional properties: (1) It employs one scaling function and two distinct wavelets, which are designed to be offset from one another by one half, (2) The double-density DWT is overcomplete by a Factor of two, and (3) It is nearly shift-invariant. In two dimensions, this transform outperforms the standard DWT in terms of denoising however, there is room for improvement because not all of the wavelets are directional. That is, although the double-density DWT utilizes more wavelets, some lack a dominant spatial orientation, which prevents them from being able to isolate those directions.
The code performs a number (ITERS) of iterations of the
Bailey s 6-step FFT algorithm (following the ideas in the
CMU Task parallel suite).
1.- Generates an input signal vector (dgen) with size
n=n1xn2 stored in row major order
In this code the size of the input signal
is NN=NxN (n=NN, n1=n2=N)
2.- Transpose (tpose) A to have it stored in column
major order
3.- Perform independent FFTs on the rows (cffts)
4.- Scale each element of the resulting array by a
Factor of w[n]**(p*q)
5.- Transpose (tpose) to prepair it for the next step
6.- Perform independent FFTs on the rows (cffts)
7.- Transpose the resulting matrix
The code requires nested Parallelism.
En este diagrama se encuentran varias curvas de rugosidad relativa constante para determinar el Factor de friccion de fanning en funcion del numero de reynolds utilizando la ecuacion de colebrook resuelta por el metodo del punto fijo.
la funcion fanning2 calcula el Factor de friccion con tan solo ingresar la rugosidad relativa y el numero de reynols.
Para generar el diagrama se debe terner la funcion fanning2.
A major societal challenge for the decades to come will be the delivery of effective
medical services while at the same time curbing the growing cost of healthcare.
It is expected that new concepts-particularly electronically assisted healthcare will
provide an answer. This will include new devices, new medical services as well
as networking. On the device side, impressive innovation has been made possible
by micro- and nanoelectronics or CMOS Integrated Circuits. Even higher accuracy
and smaller form Factor combined with reduced cost and increased convenience
of use are enabled by incorporation of CMOS IC design in the realization of biomedical
systems. The compact hearing aid devices and current pacemakers are
good examples of how CMOS ICs bring about these new functionalities and services
in the medical field. Apart from these existing applications, many researchers
are trying to develop new bio-medical solutions such as Artificial Retina, Deep
Brain Stimulation, and Wearable Healthcare Systems. These are possible by combining
the recent advances of bio-medical technology with low power CMOS IC
technology.
