為了能夠滿足基站易于選址、優質快速的建站要求和易維護、低成本、高可靠的運行要求，本文對以方艙來實現一體化結構基站做出一番探討。從系統設計的觀點闡述了移動通信高性能基站天線設計的幾個關鍵問題，介紹了智能天線技術在基站中的應用，并且用HFSS軟件仿真了一種新型的對稱陣子天線，該天線駐波比小于2的帶寬可以達到60%，具有良好的寬頻帶特性。 Abstract: In order to meet the station construction requirement of easy site selection and Fast base station， and meet the operational requirement of easy maintenance， low cost and high reliability， this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design， the application of smart antenna in base station was also introduced. And a novel dipole antenna was simulated by using HFSS， the VSWR of the antenna is less than 2， and the bandwidth was reach to 60%. So it has good broadband properties.
上傳時間： 2013-11-20
上傳用戶：linlin
同步技術是跳頻通信系統的關鍵技術之一，尤其是在快速跳頻通信系統中，常規跳頻通信通過同步字頭攜帶相關碼的方法來實現同步，但對于快跳頻來說，由于是一跳或者多跳傳輸一個調制符號，難以攜帶相關碼。對此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關碼的困難。分析了同步性能，仿真結果表明該方案同步時間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the Fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the Fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of Fast frequency hopping in carrying correlation code， a Fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in Fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
上傳時間： 2013-11-23
上傳用戶：mpquest
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as Fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-14
上傳用戶：zoudejile
Express Mode uses an 8-bit wide bus path for Fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標簽： Spartan-XL Express XAPP FPGA
上傳時間： 2015-01-02
上傳用戶：nanxia
The CoolRunner-II CPLD is a highly uniform family of Fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上傳時間： 2013-11-03
上傳用戶：1037540470
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， Fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
上一個專欄討論了執行模型和內核啟動執行配置如何影響寄存器數量以及本地多處理器資源(比如共享內存，share memo~)。現在我們繼續討論內存的性能以及共享內存在reverseArray_multiblock_Fast．CU中的使用。
標簽： 共享內存
上傳時間： 2013-10-22
上傳用戶：zaizaibang
XMDS is a code generator that integrates equations. You write them down in human readable form in a XML file, and it goes away and writes and compiles a C++ program that integrates those equations as Fast as it can possibly be done in your architecture.
標簽： integrates generator equations readable
上傳時間： 2014-11-27
上傳用戶：hebmuljb
This a separate release of the OpenSS7 X/Open XTI/TLI library, TLI modules (timod, tirdwr) and the INET driver (inet) that provides Unix98 compatible interface to Linux NET4 TCP/IP stacks, and all the necessary manpages and other documentation. Although these components are contained in our LiS and Linux Fast-STREAMS releases, this tarball configures, builds and installs these components separate from those releases.
上傳時間： 2015-03-12
上傳用戶：mikesering
最新的支持向量機工具箱，有了它會很方便 1. Find time to write a proper list of things to do! 2. Documentation. 3. Support Vector Regression. 4. Automated model selection. REFERENCES ========== [1] V.N. Vapnik, "The Nature of Statistical Learning Theory", Springer-Verlag, New York, ISBN 0-387-94559-8, 1995. [2] J. C. Platt, "Fast training of support vector machines using sequential minimal optimization", in Advances in Kernel Methods - Support Vector Learning, (Eds) B. Scholkopf, C. Burges, and A. J. Smola, MIT Press, Cambridge, Massachusetts, chapter 12, pp 185-208, 1999. [3] T. Joachims, "Estimating the Generalization Performance of a SVM Efficiently", LS-8 Report 25, Universitat Dortmund, Fachbereich Informatik, 1999.
上傳時間： 2013-12-16
上傳用戶：亞亞娟娟123
