Freescale IMX31 ADS CS8900a Head file, it is very important
標(biāo)簽： Freescale important 8900a 8900
上傳時(shí)間： 2015-07-05
上傳用戶：hj_18
Freescale IMX31 ADS board iic driver interrupt file,very important
標(biāo)簽： Freescale interrupt important driver
上傳時(shí)間： 2013-12-10
上傳用戶：zhangyigenius
Freescale IMX31 ADS Demo board backlight driver file , please be secret
標(biāo)簽： Freescale backlight driver please
上傳時(shí)間： 2013-12-19
上傳用戶：hphh
This file contains a new and improved version of the Huffman coder, (June 29. 2001). The name is Huff06.m. There are also some additional files which are helpful when using Matlab for data compression: quantizer, different variants of run-length-encoding and end-of-block coding in Mat2Vec, and a program which do JPEG-like entropy coding. A complete compression example is shown in TestMat2Vec.m. This file is all you need for Huffman coding in MatLab.
標(biāo)簽： contains improved Huffman version
上傳時(shí)間： 2015-07-05
上傳用戶：jeffery
Overview DSN-Less Connection dBASE Excel Text File Visual FoxPro Access database SQL Server Oracle MySQL AS400 Sybase Sybase SQL AnyWhere DSN Connection
標(biāo)簽： Connection Overview DSN-Less database
上傳時(shí)間： 2014-01-11
上傳用戶：努力努力再努力
標(biāo)準(zhǔn)mpeg4 File Formate ,通過學(xué)習(xí)可了解mpeg4文件得格式. 對做mpeg2 Player有幫助.
標(biāo)簽： mpeg4 Formate Player mpeg2
上傳時(shí)間： 2014-12-02
上傳用戶：wfeel
/* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm
標(biāo)簽： generates the program define
上傳時(shí)間： 2015-07-07
上傳用戶：wangchong
-- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at
標(biāo)簽： design combinational Shifter Barrel
上傳時(shí)間： 2014-12-21
上傳用戶：784533221
BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
標(biāo)簽： compatible 300 Spartan2e BurchED
上傳時(shí)間： 2015-07-07
上傳用戶：star_in_rain
verilog ADPLL file with testbench.v
標(biāo)簽： testbench verilog ADPLL file
上傳時(shí)間： 2015-07-09
上傳用戶：cx111111
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