Designing a synchronous Finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
標(biāo)簽：
synchronous
Designing
engineer
digital
上傳時(shí)間：
2014-01-17
上傳用戶：dreamboy36
