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Thinking in C++(Second Edition),Volume One:Introduction to Standard C++
國外經典C++原版書庫《C++編程思想(第2版)第1卷：標準C++導引》/(美)埃克爾(Eckel,B)著；劉宗田等譯 十分經典、難得！
標簽：
Introduction
Thinking
Standard
Edition
上傳時間：
2014-12-07
上傳用戶：jkhjkh1982
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Data Structures and Algorithms
with Object-Oriented Design Patterns in Java
Bruno R. Preiss
B.A.Sc., M.A.Sc., Ph.D., P.Eng.
Associate Professor
Department of Electrical and Computer Engineering
University of Waterloo, Waterloo, Canada
標簽：
B.A.S
R.
Object-Oriented
Algorithms
上傳時間：
2017-03-07
上傳用戶：z754970244
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該程序用以查找任意兩個整數之間的所有素數。 Prime number finder can find all primes between a and b and will write the results to the file PRIMES.TXT
標簽：
and
between
number
finder
上傳時間：
2014-01-14
上傳用戶：cccole0605
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為了改變目前電網現場作業管理的變電巡檢、變電檢修試驗、輸電線路巡檢檢修等管理系統各自獨立運行，信息不能共享，功能、效率受限，建設和維護成本高的現狀，提出了采用B/S+C/S構架模式，將各現場作業管理模塊和生產MIS（管理系統）集成為一體的現場作業管理系統的設計方案，做到各子系統和生產MIS軟硬資源共享，做到同一數據唯一入口、一處錄入多處使用。各子系統設備人員等基礎信息來源于生產管理系統，各子系統又是生產管理系統的作業數據、缺陷信息的重要來源。經過研究試用成功和推廣應用，目前該系統已在江西電網220 kV及以上變電站全面應用。
Abstract:
In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t share the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and share the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.
標簽：
電網
信息化
管理系統
上傳時間：
2013-11-15
上傳用戶：han_zh
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All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標簽：
Signal
Input
Fall
Rise
上傳時間：
2013-10-23
上傳用戶：copu
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WHAT MIME64 IS: MIME64 is an encoding described in RFC1341 as MIME base64.Its purpose is to encode binary files into ASCII so that they may be passedthrough e-mail gates. In this regard, MIME64 is similar to UUENCODE.Although most binaries these days are transmitted using UUENCODE, Ihave seen a few using MIME64, and I have had requests from friends thatI decode MIME64 files that have fallen into their hands. As long assome MIME64 continues to exist, a package such as this one is usefulto have.
標簽：
MIME
described
64
encoding
上傳時間：
2013-12-17
上傳用戶：maizezhen
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Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
標簽：
representation
Magnitude
the
magnitude
上傳時間：
2013-12-24
上傳用戶：金宜
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I think this the first time every one can look at a PE crypter source
in top level language such VC++.
So as I promised ... if some one sent me one nice compress source I would
publish my source.
I dedicate this source to all people who involve in this field.
I hope it helps someone.
Have good days
ashkbiz
Check: yodap.cjb.net
標簽：
language
crypter
source
think
上傳時間：
2013-12-29
上傳用戶：dianxin61
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Ink Blotting
One method for escaping from a maze is via ‘ink-blotting’. In this method your starting square
is marked with the number ‘1’. All free, valid squares north, south, east and west around the
number ‘1‘ are marked with a number ‘2’. In the next step, all free, valid squares around the two
are marked with a ‘3’ and the process is repeated iteratively until :
The exit is found (a free square other than the starting position is reached on the very edge
of the maze), or,
No more free squares are available, and hence no exit is possible.
標簽：
method
ink-blotting
Blotting
escaping
上傳時間：
2014-12-03
上傳用戶：123啊
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基于verilog HDL的自動售貨機控制電路設計:
可以對5種不同種類的貨物進行自動售貨,價格分別為A=1.00,B=1.50,C=1.80,D=3.10,E=5.00 。售貨機可以接受1元,5角,1角三種硬幣(即有三種輸入信號IY,IWJ,IYJ),并且在一個3位7段LED(二位代表元,一位代表角)顯示以投入的總錢數，最大9.90元，如果大于該數值，新投入的硬幣會退出,選擇貨物的輸入信號Ia,Ib,Ic,Id,Ie和一個放棄信號In,輸出指示信號為 Sa, Sb ,Sc ,Sd, Se 分別表示售出相應的貨物,同時輸出的信號yuan, jiao代表找零,相應每個脈沖代表找零相應的硬幣，上述輸入和輸出信號均是一個固定寬度的脈沖信號。
標簽：
verilog
1.00
1.50
1.80
上傳時間：
2016-07-12
上傳用戶：lanwei
