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  • 蘇泊爾C21S02-B電磁爐電路圖

    蘇泊爾C21S02-B電磁爐電路圖,紅線標注,重點模塊說明!

    標簽: 21 02 蘇泊爾 電磁爐電路圖

    上傳時間: 2013-06-22

    上傳用戶:huangzr5

  • ADS-B接收機DIY全套資料

    制作基于PIC Mcu 的ADS-B接收機的全套資料,包括SCH、PCB、源碼和PC端軟件。

    標簽: ADS-B DIY 接收機

    上傳時間: 2013-04-24

    上傳用戶:cx111111

  • an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysi

    1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis\r\n2. fpga implemention of a median filter\r\n3. fpga implementation of digital filters\r\n4.hardware acceleration of edge detection algorithm on fpgas

    標簽: implementation reconstruction hyperspectral algorithm

    上傳時間: 2013-08-07

    上傳用戶:ytulpx

  • On the design of an FPGA-Based OFDM modulator for IEEE 802.11a

    On the design of an FPGA-Based OFDM modulator for IEEE 802.11a

    標簽: FPGA-Based modulator 802.11 design

    上傳時間: 2013-09-02

    上傳用戶:zjwangyichao

  • 2012TI杯陜西賽題B題--頻率補償電路

    2012TI杯陜西賽題H題,2012TI杯陜西賽題B題--頻率補償電路.

    標簽: 2012 TI 頻率補償電路

    上傳時間: 2013-10-07

    上傳用戶:ysystc670

  • PSHLY-B回路電阻測試儀

    PSHLY-B回路電阻測試儀介紹

    標簽: PSHLY-B 回路 電阻測試儀

    上傳時間: 2013-11-05

    上傳用戶:木子葉1

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    標簽: Signal Input Fall Rise

    上傳時間: 2013-10-23

    上傳用戶:copu

  • TKS仿真器B系列快速入門

    TKS仿真器B系列快速入門

    標簽: TKS 仿真器 快速入門

    上傳時間: 2013-10-31

    上傳用戶:aix008

  • 一個簡單好用的B+樹算法實現(xiàn)

    一個簡單好用的B+樹算法實現(xiàn)

    標簽: 算法

    上傳時間: 2015-01-04

    上傳用戶:縹緲

  • 一個用Basic實現(xiàn)的B-Tree算法

    一個用Basic實現(xiàn)的B-Tree算法

    標簽: B-Tree Basic 算法

    上傳時間: 2013-12-30

    上傳用戶:ccclll

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