last time when i came here to find some clock references. but most of them can not works well. so this files works well on FPGA board.
標簽： references clock works last
上傳時間： 2015-11-07
上傳用戶：baitouyu
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間： 2014-08-16
上傳用戶：adada
針對傳統集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現NCO模塊，在下變頻模塊調用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調的原理和實現方法，推導出一種簡便的引入?仔/4固定相移的實現方法。采用模塊化的設計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發板上成功實現了整個系統。測試結果表明該系統正確實現了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-06
上傳用戶：liu123
Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
標簽： Raggedstone1 development Spartan3 low-cost
上傳時間： 2013-12-02
上傳用戶：lps11188
資料共6.37G，Xilinx Z-turn Board zynq7020平臺，包括FPGA、SDK源碼，例程源碼，各種圖像處理，人工智能算法，原理圖，PCB，適合做項目移植、項目開發
上傳時間： 2021-12-20
上傳用戶：
利用FPGA的51 ，IP核實現與單片機和ARM的串口通信
上傳時間： 2013-08-05
上傳用戶：lalaruby
基于FPGA數字頻率計的實現，文中有所有的源代碼，僅供參考。
上傳時間： 2013-08-05
上傳用戶：13736136189
學習FPGA的不錯的文章,有利于自己設計和編寫程序
標簽： FPGA
上傳時間： 2013-08-05
上傳用戶：xjz632
基FPGA Cyclone II_EP2C5 EP2C8的頻率計
上傳時間： 2013-08-05
上傳用戶：Thuan
波束成型，基于FPGA的波束成型，包括兩個文件，一個濾波器，一個xilinx仿真
上傳時間： 2013-08-05
上傳用戶：joheace
<bdo id="sk44m"></bdo>