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This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
針對嵌入式機器視覺系統向獨立化、智能化發展的要求，介紹了一種嵌入式視覺系統--智能相機。基于對智能相機體系結構、組成模塊和圖像采集、傳輸和處理技術的分析，對國內外的幾款智能相機進行比較。綜合技術發展現狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機的發展方向。分析結果表明，該系統設計可以實現脫離PC運行，完成圖像獲取與分析，并作出相應輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
上傳時間： 2013-10-24
上傳用戶：bvdragon
The XPS Ethernetlite peripheral does not provide any mechanism to access the Ethernet PHYregisters. These registers are used to configure auto negotiation parameters and to obtain PHYstatus. This application note provides reference systems and associated software to accessPHY registers by connecting the serial management bus signals MDC and MDIO to GPIOswhich the software controls directly.
上傳時間： 2013-10-17
上傳用戶：JamesB
為提升虛擬儀器傳輸速率與實時性能，擴展監測范圍，在VC的軟件平臺上設計了一種全功能虛擬示波器。與傳統虛擬示波器相比，該系統采用嵌入式系統完成信號采集，采用工業以太網為傳輸介質，通過線性插值算法和多線程編程思想，實現波形顯示、參數計算、頻譜分析以及波形存儲及回放功能。實驗結果表明，該虛擬示波器可以實現20 kHz采樣頻率下的波形精確顯示，達到預期的各項指標。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
上傳時間： 2013-11-25
上傳用戶：wbwyl
Abstract: This reference design provides design ideas for a cost-effective, low-power liquid-level measurement dataacquisition system (DAS) using a compensated silicon pressure sensor and a high-precision delta-sigma ADC. Thisdocument discusses how to select the compensated silicon pressure sensor, suggest system algorithms, and providenoise analyses. It also describes calibration ideas to improve system performance while also reducing complexity andcost.
上傳時間： 2013-10-08
上傳用戶：sjy1991
[linux的內核及其內核源碼分析].U-Boot.Quick.Reference
標簽： Reference U-Boot linux Quick
上傳時間： 2013-11-13
上傳用戶：frank1234
The Linux Programming Interface - A Linux and UNIX System
標簽： Programming Linux Interface Handbook
上傳時間： 2013-11-10
上傳用戶：asdstation
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).
上傳時間： 2014-12-22
上傳用戶：xanxuan
GCC 中文手冊
標簽： GCC
上傳時間： 2013-11-20
上傳用戶：woshiayin
This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
上傳時間： 2013-10-29
上傳用戶：旭521
