java applet code for Generating RSA key pair
標簽： Generating applet java code
上傳時間： 2014-08-15
上傳用戶：manking0408
For Generating wind speed model in ARMA
標簽： Generating speed model ARMA
上傳時間： 2017-06-25
上傳用戶：
XML parser with DOM. Helps on parsing and Generating a directory structure
標簽： Generating directory structure parsing
上傳時間： 2014-12-06
上傳用戶：ywqaxiwang
遞歸法生成2D迷宮,Recursive method Generating 2D maze
標簽： Generating Recursive method maze
上傳時間： 2017-07-09
上傳用戶：libinxny
guitar tunner... useful for Generating varius tunes
標簽： Generating guitar tunner useful
上傳時間： 2013-12-21
上傳用戶：181992417
Generating histogram
標簽： Generating histogram
上傳時間： 2017-07-20
上傳用戶：BIBI
Generating Jasper Reports with Java
標簽： Generating Reports Jasper Java
上傳時間： 2014-01-20
上傳用戶：牧羊人8920
·詳細說明：雙音多頻（DTMF）信號發生器的使用源程序，vc 編寫，與《雙音多頻（DTMF）接收器的使用源程序》聯合用- The double sound multi- frequencies (DTMF) the signal Generating device use source program, the vc compilation, (DTMF) Receiver Use Source p
上傳時間： 2013-07-23
上傳用戶：tianjinfan
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for Generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上傳時間： 2013-10-25
上傳用戶：banyou
The purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-up DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-up DC-DC converter (capable of Generating up to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input supply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).
上傳時間： 2014-12-23
上傳用戶：781354052
