基于變頻調(diào)速的水平連鑄機(jī)拉坯輥速度控制系統(tǒng)Frequency Inverter Based Drawing RollerS peedC ontrolSy stem ofHorizontal Continuous Casting MachineA 偉劉沖旅巴(南 華 大 學(xué)電氣工程學(xué)院，衡陽(yáng)421001)摘要拉坯輥速度控制是水平連鑄工藝的關(guān)鍵技術(shù)之一，采用變頻器實(shí)現(xiàn)水平連鑄機(jī)拉坯輥速度程序控制，由信號(hào)發(fā)生裝置給變頻器提供程控信號(hào)?，F(xiàn)場(chǎng)應(yīng)用表明該控制系統(tǒng)速度響應(yīng)快，控制精度高，滿足了水平連鑄生產(chǎn)的需要。關(guān)鍵詞水平連鑄拉坯輥速度程序控制變頻器Absh'act Speedc ontorlof dr awingor leris on eo fth ek eyte chnologiesfo rho rizontalco ntinuousca stingm achine.Fo rth ispu rpose,fr equencyco nverterisad optedfo rdr awingor lersp eedp rogrammablec ontorlof ho rizontalco ntinuousca stingm achine,th ep rogrammableco ntorlsi gnalto fr equencyc onverteris provided場(chǎng)a signal Generator. The results of application show that the response of system is rapid and the control accuracy is high enough to meet thedemand of production of horizontal continuous casting.Keywords Horizontalco ntinuousc asting Drawingor ler Speedp rogrammablec ontrol Ferquencyin verter 隨著 現(xiàn) 代 化工業(yè)生產(chǎn)對(duì)鋼材需求量的日益增加，連鑄生產(chǎn)能力已經(jīng)成為衡量一個(gè)國(guó)家冶金工業(yè)發(fā)展水平的重要指標(biāo)之一。近十幾年來(lái)，水平連鑄由于具有投資少、鑄坯直、見效快等多方面的優(yōu)點(diǎn)，國(guó)內(nèi)許多鋼鐵企業(yè)利用水平連鑄機(jī)來(lái)澆鑄特種合金鋼，發(fā)揮了其獨(dú)特的優(yōu)勢(shì)并取得了較好的經(jīng)濟(jì)效益〔1,2)0采用 水 平 連鑄機(jī)澆鑄特種合金鋼時(shí)，由于拉坯機(jī)是水平連鑄系統(tǒng)中的關(guān)鍵設(shè)備之一，拉坯機(jī)及其控制性能的好壞直接影響著連鑄坯的質(zhì)量，因此，連鑄的拉坯技術(shù)便成為整個(gè)水平連鑄技術(shù)的核心。由于鋼的冶煉過程是在高溫下進(jìn)行的，鋼水溫度的變化又容易影響鑄坯的質(zhì)量和成材率，因此，如何能在高溫環(huán)境下控制好與鑄坯速度相關(guān)的參數(shù)(拉、推程量，中停時(shí)間和拉坯頻率等)對(duì)于確保連鑄作業(yè)的進(jìn)一步高效化，延長(zhǎng)系統(tǒng)的連續(xù)作業(yè)時(shí)間十分關(guān)鍵。因此，拉坯輥速度控制技術(shù)是連鑄生產(chǎn)過程控制領(lǐng)域中的關(guān)鍵技術(shù)之- [31
標(biāo)簽： 變頻調(diào)速 水平連鑄機(jī) 速度控制
上傳時(shí)間： 2013-10-12
上傳用戶：gxy670166755
在綜合分析諧波勵(lì)磁無(wú)刷同步發(fā)電機(jī)勵(lì)磁控制系統(tǒng)的基礎(chǔ)上,對(duì)其勵(lì)磁控制策略進(jìn)行了研究,開發(fā)了一套基于DSP( TMS320F2812) 控制的新型柴油發(fā)電機(jī)勵(lì)磁控制系統(tǒng),該系統(tǒng)采用參數(shù)自適應(yīng)模糊PID 控制勵(lì)磁,選用交流采樣方式實(shí)時(shí)檢測(cè)各信號(hào)的瞬時(shí)特性,系統(tǒng)仿真結(jié)果以及在1 臺(tái)25 kW 工頻柴油發(fā)電機(jī)上的試驗(yàn)結(jié)果證明了該控制器具有較好的電壓調(diào)節(jié)特性,系統(tǒng)穩(wěn)態(tài)和暫態(tài)性能完全滿足發(fā)電機(jī)對(duì)勵(lì)磁系統(tǒng)的要求。關(guān)鍵詞:勵(lì)磁調(diào)節(jié);模糊PID 控制;數(shù)字信號(hào)處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous Generator and it s characteristics ,a new type of diesel Generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel Generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the Generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
標(biāo)簽： DSP 柴油發(fā)電機(jī) 勵(lì)磁控制 系統(tǒng)研究
上傳時(shí)間： 2013-10-29
上傳用戶：fxf126@126.com
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern Generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
針對(duì)Virtex-6 給出了HDL設(shè)計(jì)指南，其中，賽靈思為每個(gè)設(shè)計(jì)元素給出了四個(gè)設(shè)計(jì)方案元素，并給出了Xilinx認(rèn)為是最適合你的解決方案。這4個(gè)方案包括：實(shí)例，推理，CORE Generator或者其他Wizards，宏支持.
標(biāo)簽： Virtex HDL 設(shè)計(jì)指南
上傳時(shí)間： 2013-11-07
上傳用戶：gy592333
本文對(duì)數(shù)字基帶信號(hào)脈沖成型濾波的應(yīng)用、原理及實(shí)現(xiàn)進(jìn)行了研究。首先介紹了數(shù)字成型濾波的應(yīng)用意義并分析了模擬和數(shù)字兩種硬件實(shí)現(xiàn)方法，接著介紹了成形濾波器設(shè)計(jì)所需要MATLAB軟件，以及利用ISE system Generator在FPGA上進(jìn)行濾波器實(shí)現(xiàn)的優(yōu)勢(shì)。文中給出了成形濾波函數(shù)的數(shù)學(xué)模型，討論了幾種常用成形濾波函數(shù)的傳輸特性以及對(duì)傳輸系統(tǒng)信號(hào)誤碼率的影響。然后介紹了本次設(shè)計(jì)中使用到的數(shù)字成形濾波器設(shè)計(jì)的幾種FIR濾波器結(jié)構(gòu)。把各種設(shè)計(jì)方案進(jìn)行仿真，比較仿真結(jié)果，最后根據(jù)實(shí)際應(yīng)用的情況并結(jié)合設(shè)計(jì)仿真中出現(xiàn)的問題進(jìn)行分析，得出各種設(shè)計(jì)結(jié)構(gòu)的優(yōu)缺點(diǎn)以及適合應(yīng)用的場(chǎng)合。
標(biāo)簽： FPGA 數(shù)字 成形 濾波器設(shè)計(jì)
上傳時(shí)間： 2013-10-18
上傳用戶：aesuser
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern Generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
針對(duì)Virtex-6 給出了HDL設(shè)計(jì)指南，其中，賽靈思為每個(gè)設(shè)計(jì)元素給出了四個(gè)設(shè)計(jì)方案元素，并給出了Xilinx認(rèn)為是最適合你的解決方案。這4個(gè)方案包括：實(shí)例，推理，CORE Generator或者其他Wizards，宏支持.
標(biāo)簽： Virtex HDL 設(shè)計(jì)指南
上傳時(shí)間： 2015-01-02
上傳用戶：pinksun9
本文對(duì)數(shù)字基帶信號(hào)脈沖成型濾波的應(yīng)用、原理及實(shí)現(xiàn)進(jìn)行了研究。首先介紹了數(shù)字成型濾波的應(yīng)用意義并分析了模擬和數(shù)字兩種硬件實(shí)現(xiàn)方法，接著介紹了成形濾波器設(shè)計(jì)所需要MATLAB軟件，以及利用ISE system Generator在FPGA上進(jìn)行濾波器實(shí)現(xiàn)的優(yōu)勢(shì)。文中給出了成形濾波函數(shù)的數(shù)學(xué)模型，討論了幾種常用成形濾波函數(shù)的傳輸特性以及對(duì)傳輸系統(tǒng)信號(hào)誤碼率的影響。然后介紹了本次設(shè)計(jì)中使用到的數(shù)字成形濾波器設(shè)計(jì)的幾種FIR濾波器結(jié)構(gòu)。把各種設(shè)計(jì)方案進(jìn)行仿真，比較仿真結(jié)果，最后根據(jù)實(shí)際應(yīng)用的情況并結(jié)合設(shè)計(jì)仿真中出現(xiàn)的問題進(jìn)行分析，得出各種設(shè)計(jì)結(jié)構(gòu)的優(yōu)缺點(diǎn)以及適合應(yīng)用的場(chǎng)合。
標(biāo)簽： FPGA 數(shù)字 成形 濾波器設(shè)計(jì)
上傳時(shí)間： 2013-10-22
上傳用戶：tyler
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern Generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽： RocketIO Virtex XAPP 713
上傳時(shí)間： 2013-12-25
上傳用戶：jkhjkh1982
在Multisim 10軟件環(huán)境下，設(shè)計(jì)一種由運(yùn)算放大器構(gòu)成的精確可控矩形波信號(hào)發(fā)生器，結(jié)合系統(tǒng)電路原理圖重點(diǎn)闡述了各參數(shù)指標(biāo)的實(shí)現(xiàn)與測(cè)試方法。通過改變RC電路的電容充、放電路徑和時(shí)間常數(shù)實(shí)現(xiàn)了占空比和頻率的調(diào)節(jié)，通過多路開關(guān)投入不同數(shù)值的電容實(shí)現(xiàn)了頻段的調(diào)節(jié)，通過電壓取樣和同相放大電路實(shí)現(xiàn)了輸出電壓幅值的調(diào)節(jié)并提高了電路的帶負(fù)載能力，可作為頻率和幅值可調(diào)的方波信號(hào)發(fā)生器。Multisim 10仿真分析及應(yīng)用電路測(cè)試結(jié)果表明，電路性能指標(biāo)達(dá)到了設(shè)計(jì)要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal Generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal Generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
標(biāo)簽： Multisim 矩形波 信號(hào)發(fā)生器 仿真
上傳時(shí)間： 2014-01-21
上傳用戶：shen007yue
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