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Generator

基于變頻調速的水平連鑄機拉坯輥速度控制系統

基于變頻調速的水平連鑄機拉坯輥速度控制系統Frequency Inverter Based Drawing RollerS peedC ontrolSy stem ofHorizontal Continuous Casting MachineA 偉劉沖旅巴(南華大學電氣工程學院，衡陽421001)摘要拉坯輥速度控制是水平連鑄工藝的關鍵技術之一，采用變頻器實現水平連鑄機拉坯輥速度程序控制，由信號發生裝置給變頻器提供程控信號。現場應用表明該控制系統速度響應快，控制精度高，滿足了水平連鑄生產的需要。關鍵詞水平連鑄拉坯輥速度程序控制變頻器Absh'act Speedc ontorlof dr awingor leris on eo fth ek eyte chnologiesfo rho rizontalco ntinuousca stingm achine.Fo rth ispu rpose,fr equencyco nverterisad optedfo rdr awingor lersp eedp rogrammablec ontorlof ho rizontalco ntinuousca stingm achine,th ep rogrammableco ntorlsi gnalto fr equencyc onverteris provided場a signal Generator. The results of application show that the response of system is rapid and the control accuracy is high enough to meet thedemand of production of horizontal continuous casting.Keywords Horizontalco ntinuousc asting Drawingor ler Speedp rogrammablec ontrol Ferquencyin verter 隨著現代化工業生產對鋼材需求量的日益增加，連鑄生產能力已經成為衡量一個國家冶金工業發展水平的重要指標之一。近十幾年來，水平連鑄由于具有投資少、鑄坯直、見效快等多方面的優點，國內許多鋼鐵企業利用水平連鑄機來澆鑄特種合金鋼，發揮了其獨特的優勢并取得了較好的經濟效益〔1,2)0采用水平連鑄機澆鑄特種合金鋼時，由于拉坯機是水平連鑄系統中的關鍵設備之一，拉坯機及其控制性能的好壞直接影響著連鑄坯的質量，因此，連鑄的拉坯技術便成為整個水平連鑄技術的核心。由于鋼的冶煉過程是在高溫下進行的，鋼水溫度的變化又容易影響鑄坯的質量和成材率，因此，如何能在高溫環境下控制好與鑄坯速度相關的參數(拉、推程量，中停時間和拉坯頻率等)對于確保連鑄作業的進一步高效化，延長系統的連續作業時間十分關鍵。因此，拉坯輥速度控制技術是連鑄生產過程控制領域中的關鍵技術之- [31

標簽： 變頻調速水平連鑄機速度控制

上傳時間： 2013-10-12

上傳用戶：gxy670166755
基于DSP的新型柴油發電機勵磁控制系統研究

在綜合分析諧波勵磁無刷同步發電機勵磁控制系統的基礎上,對其勵磁控制策略進行了研究,開發了一套基于DSP( TMS320F2812) 控制的新型柴油發電機勵磁控制系統,該系統采用參數自適應模糊PID 控制勵磁,選用交流采樣方式實時檢測各信號的瞬時特性,系統仿真結果以及在1 臺25 kW 工頻柴油發電機上的試驗結果證明了該控制器具有較好的電壓調節特性,系統穩態和暫態性能完全滿足發電機對勵磁系統的要求。關鍵詞:勵磁調節;模糊PID 控制;數字信號處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous Generator and it s characteristics ,a new type of diesel Generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel Generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the Generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling

標簽： DSP 柴油發電機勵磁控制系統研究

上傳時間： 2013-10-29

上傳用戶：fxf126@126.com
XAPP740利用AXI互聯設計高性能視頻系統

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern Generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

標簽： XAPP 740 AXI 互聯

上傳時間： 2013-11-14

上傳用戶：fdmpy
Virtex-6 的HDL設計指南

針對Virtex-6 給出了HDL設計指南，其中，賽靈思為每個設計元素給出了四個設計方案元素，并給出了Xilinx認為是最適合你的解決方案。這4個方案包括：實例，推理，CORE Generator或者其他Wizards，宏支持.

標簽： Virtex HDL 設計指南

上傳時間： 2013-11-07

上傳用戶：gy592333
數字成形濾波器設計及FPGA實現

本文對數字基帶信號脈沖成型濾波的應用、原理及實現進行了研究。首先介紹了數字成型濾波的應用意義并分析了模擬和數字兩種硬件實現方法，接著介紹了成形濾波器設計所需要MATLAB軟件，以及利用ISE system Generator在FPGA上進行濾波器實現的優勢。文中給出了成形濾波函數的數學模型，討論了幾種常用成形濾波函數的傳輸特性以及對傳輸系統信號誤碼率的影響。然后介紹了本次設計中使用到的數字成形濾波器設計的幾種FIR濾波器結構。把各種設計方案進行仿真，比較仿真結果，最后根據實際應用的情況并結合設計仿真中出現的問題進行分析，得出各種設計結構的優缺點以及適合應用的場合。

標簽： FPGA 數字成形濾波器設計

上傳時間： 2013-10-18

上傳用戶：aesuser
XAPP740利用AXI互聯設計高性能視頻系統

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern Generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

標簽： XAPP 740 AXI 互聯

上傳時間： 2013-11-23

上傳用戶：shen_dafa
Virtex-6 的HDL設計指南

針對Virtex-6 給出了HDL設計指南，其中，賽靈思為每個設計元素給出了四個設計方案元素，并給出了Xilinx認為是最適合你的解決方案。這4個方案包括：實例，推理，CORE Generator或者其他Wizards，宏支持.

標簽： Virtex HDL 設計指南

上傳時間： 2015-01-02

上傳用戶：pinksun9
數字成形濾波器設計及FPGA實現

本文對數字基帶信號脈沖成型濾波的應用、原理及實現進行了研究。首先介紹了數字成型濾波的應用意義并分析了模擬和數字兩種硬件實現方法，接著介紹了成形濾波器設計所需要MATLAB軟件，以及利用ISE system Generator在FPGA上進行濾波器實現的優勢。文中給出了成形濾波函數的數學模型，討論了幾種常用成形濾波函數的傳輸特性以及對傳輸系統信號誤碼率的影響。然后介紹了本次設計中使用到的數字成形濾波器設計的幾種FIR濾波器結構。把各種設計方案進行仿真，比較仿真結果，最后根據實際應用的情況并結合設計仿真中出現的問題進行分析，得出各種設計結構的優缺點以及適合應用的場合。

標簽： FPGA 數字成形濾波器設計

上傳時間： 2013-10-22

上傳用戶：tyler
XAPP713 -Virtex-4 RocketIO誤碼率測試器

The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern Generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).

標簽： RocketIO Virtex XAPP 713

上傳時間： 2013-12-25

上傳用戶：jkhjkh1982
基于Multisim 10的矩形波信號發生器仿真與實現

在Multisim 10軟件環境下，設計一種由運算放大器構成的精確可控矩形波信號發生器，結合系統電路原理圖重點闡述了各參數指標的實現與測試方法。通過改變RC電路的電容充、放電路徑和時間常數實現了占空比和頻率的調節，通過多路開關投入不同數值的電容實現了頻段的調節，通過電壓取樣和同相放大電路實現了輸出電壓幅值的調節并提高了電路的帶負載能力，可作為頻率和幅值可調的方波信號發生器。Multisim 10仿真分析及應用電路測試結果表明，電路性能指標達到了設計要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal Generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal Generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.

標簽： Multisim 矩形波信號發生器仿真

上傳時間： 2014-01-21

上傳用戶：shen007yue