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HIGH-speed

  • C8051F020

    HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C

    標簽: C8051F020

    上傳時間: 2013-10-12

    上傳用戶:lalalal

  • 基于AVR的新型防汽車追尾安全裝置設計

    針對目前汽車追尾事件頻發問題,提出一種防汽車車前和車后追尾的安全裝置設計。該設計以高性能、低功耗的8位AVR微處理器ATmega8L為核心,結合霍爾式車速傳感器、激光雷達測距裝置和MMA7260QT加速度傳感器,能夠兼顧車前和車后,摒棄以往設計中只考慮車前或車后單一性缺點,尤其適用于高速、夜晚或新手行車。 Abstract:  Aiming at the high frequency of vehicle rear-end collision,a safe device design of anti-vehicle rear-end collision is presented.In the design,the high-performance,low-power8-bit AVR microprocessor ATmega8L is utilized as a core combined with Hall-type speed sensor,laser-radar ranging devices and the acceleration sensor MMA7260QT.The design considers both the front and back of a car,and overcomes the drawbacks of former designs in which only the front or the back of the car is considered,so it is especially suitable for HIGH-speed,night or the beginner’s driving.

    標簽: AVR 汽車追尾 裝置

    上傳時間: 2013-10-14

    上傳用戶:GavinNeko

  • 基于C8051F320的心電監護系統設計

    介紹一種基于C8051單片機的動態心電監護系統。該系統由兩部分組成:以C8051F320單片機為核心的數據采集裝置和以PC機為平臺的分析處理系統。硬件電路功耗低,由單片機自帶的USB接口將數據傳送給PC機。軟件平臺采用LabVIEW可視化虛擬儀器系統開發平臺,將傳統儀器的功能模塊集成到計算機中,用戶可通過修改虛擬儀器的程序改變其功能。采用USB接口實時傳輸心電數據,并將數據采集模塊設計為計算機外設,使該系統高速快捷、小巧便攜。 Abstract:  In this design,a low-cost ECG electrocardiogram monitoring system is introduced,which consists of two parts:data acquisition device based on C8051F320and PC terminal as the analysis and processing system.The system is low-power consumption,the data is transmitted to the PC terminal by USB interface of the C8051F320.By using the visible virtual instrument system developing platform LabVIEW,the traditional instruments function modules are integrated into the computer,so the user can modify virtual instrument software to change its function to meet their needs.Using USB in-terface to realize real-time ECG data transmission,in addition,ECG data acquisition module is designed as the computer peripheral,which makes the syetem HIGH-speed and portable.

    標簽: C8051F320 心電監護 系統設計

    上傳時間: 2013-11-13

    上傳用戶:zhangzhenyu

  • 基于AVR單片機的USB接口設計

    以AVR單片機ATmega8和USB接口器件PDIUSBD12為核心,基于標準的USB1.1協議,設計一種通用USB接口模塊,以滿足嵌入式系統中對USB接口的需求。對模塊的硬件電路或單片機固件程序的硬件接口層稍加修改即可用于其他各種微處理器。該模塊可為各種嵌入式系統增加USB接口,實現與USB主機系統通信。 Abstract:  Based on AVR microcontroller ATmega8 and USB interface chip PDIUSBD12, a general USB interface module is designed according to USB1.1 protocol for various requirements of embedded systems. Only with few modifications in circuit or hardware abstract layer of firmware, the module can be used on many types of microprocessors. All kinds of embedded systems can realize high speed and stable communication with USB host systems, owing to the facility of this module.

    標簽: AVR USB 單片機 接口設計

    上傳時間: 2014-01-08

    上傳用戶:趙云興

  • 基于STC12C5408AD的記憶示波器

    主要介紹構成記憶示波器的STC12C5408AD增強型單片機8通道10位模數轉換功能的設置、應用和具體的匯編程序設計,以及PC機串行通訊和圖形顯示的高速匯編程序的設計要點,并列舉實例說明其應用效果。 Abstract:  The configuration, applications and the designs for? compiling program of the memorial oscillograph of 10 bits A/D conversation are introduced. It’s bases on STC12C5408AD 8? channels? single-chip? computer? in? enhancement? mode. It also recommends the devising essentials of high speed compiling program for PC serial communication and graphics display, lists examples to explain its effects in using.

    標簽: C5408 5408 STC 12C

    上傳時間: 2013-10-10

    上傳用戶:adada

  • lpc2478完全使用手冊

    NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip HIGH-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.

    標簽: 2478 lpc 使用手冊

    上傳時間: 2013-11-15

    上傳用戶:zouxinwang

  • PCA82C250 PCA82C251 CAN Transc

    The PCA82C250 and PCA82C251 are advanced transceiver products for use in automotive and general industrialapplications with transfer rates up to 1 Mbit/s. They support the differential bus signal representation beingdescribed in the international standard for in-vehicle CAN HIGH-speed applications (ISO 11898). Controller AreaNetwork (CAN) is a serial bus protocol being primarily intended for transmission of control related data between anumber of bus nodes.

    標簽: PCA 82C Transc 82

    上傳時間: 2013-11-24

    上傳用戶:Alick

  • PCA9549 Octal bus switch with

    The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.

    標簽: switch Octal 9549 with

    上傳時間: 2014-11-22

    上傳用戶:xcy122677

  • Adding 32 KB of Serial SRAM to

    Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for HIGH-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.

    標簽: Adding Serial SRAM 32

    上傳時間: 2013-10-14

    上傳用戶:cxl274287265

  • XAPP1065 - 利用Spartan-6 FPGA設計擴頻時鐘發生器

      Consumer display applications commonly use HIGH-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.

    標簽: Spartan XAPP 1065 FPGA

    上傳時間: 2014-12-28

    上傳用戶:yan2267246

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