Harvard教授Gray所寫的統計信號處理
上傳時間： 2015-02-03
上傳用戶：小草123
幾款單片機的原理介紹 主要單片機的介紹1. ATMEL公司的AVR單片機,是增強型RISC內載Flash的單片機,芯片上的Flash存儲器附在用戶的產品中,可隨時編程,再編程,使用戶的產品設計容易,更新換代方便.AVR單片機采用增強的RISC結構,使其具有高速處理能力,在一個時鐘周期內可執行復雜的指令,每MHz可實現1MIPS的處理能力.AVR單片機工作電壓為2.7~6.0V,可以實現耗電最優化.AVR的單片機廣泛應用于計算機外部設備,工業實時控制,儀器儀表,通訊設備,家用電器,宇航設備等各個領域. 2. Motorola單片機: Motorola是世界上最大的單片機廠商.從M6800開始,開發了廣泛的品種,4位,8位,16位32位的單片機都能生產,其中典型的代表有:8位機M6805,M68HC05系列,8位增強型M68HC11,M68HC12 , 16位機M68HC16, 32位機M683XX. Motorola單片機的特點之一是在同樣的速度下所用的時鐘頻率較Intel類單片機低得多,因而使得高頻噪聲低,抗干擾能力強,更適合于工控領域及惡劣的環境 . 3. MicroChip單片機: MicroChip單片機的主要產品是PIC 16C系列和17C系列8位單片機,CPU采用RISC結構,分別僅有33,35,58條指令,采用Harvard雙總線結構,運行速度快,低工作電壓,低功耗,較大的輸入輸出直接驅動能力,價格低,一次性編程,小體積. 適用于用量大,檔次低,價格敏感的產品.在辦公自動化設備,消費電子產品,電訊通信,智能儀器儀表,汽車電子,金融電子,工業控制不同領域都有廣泛的應用,PIC系列單片機在世界單片機市場份額排名中逐年提高.發展非常迅速.實達高奇電子科技有限公司: www.goldenchip.com.cn 代理PIC系列單片機.
標簽： 單片機
上傳時間： 2014-12-27
上傳用戶：鳳臨西北
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
上傳時間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs.
標簽： TMS 320 fixed-point processor
上傳時間： 2013-12-27
上傳用戶：宋桃子
The NCTUns network simulator and emulator is developed at NCTU, Taiwan. Its predecessor is the Harvard network simulator (invented by Prof. S.Y. Wang in 1999). By using a novel simulation methodology, it can do several tasks that traditional network simulators cannot easily do.
標簽： predecessor developed simulator emulator
上傳時間： 2014-12-02
上傳用戶：txfyddz
pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
標簽： outstanding S3C2440A features pccard
上傳時間： 2013-12-24
上傳用戶：lizhen9880
