The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx signals permits interfacing ofthe P82B96 with other bus systems which separate the forwardoutput path, from the backward input signal path.
The P90CL301 is a highly integrated 16/32 bit micro-controller especially suitable for applications requiring lowvoltage and low power consumption. It is fully software compatible with the 68000. Furthermore, it provides bothstandard as well as advanced peripheral functions on-chip.One of these peripheral functions is the I2C bus. This report describes worked-out driver software (written in C) toprogram the P90CL301 I2C interface. It also contains interface software routines offering the user a quick start inwriting a complete I2C system application.
The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.
Presents short and simple I2C software routines that support onlyslave (rather than master or master & slave) operation and an ASMdemonstration program. The slave-only software in this app notecomplements the master mode software presented in AN464, Usingthe 87LPC76X microcontroller as an I2C bus master.
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
