The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時(shí)間： 2013-11-24
上傳用戶(hù)：18707733937
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：shen_dafa
Semiconductor memory, card readers, microprocessors,disc drives, piezoelectric devices and digitally based systemsfurnish transient loads that a voltage regulator mustservice. Ideally, regulator output is invariant during a loadtransient. In practice, some variation is encountered andbecomes problematic if allowable operating voltage tolerancesare exceeded. This mandates testing the regulatorand its associated support components to verify desiredperformance under transient loading conditions. Variousmethods are employable to generate transient loads, allowingobservation of regulator response
標(biāo)簽： 如何測(cè)試 穩(wěn)壓器 瞬態(tài)響應(yīng) 負(fù)載
上傳時(shí)間： 2013-11-21
上傳用戶(hù)：semi1981
本程序集是Allen I. Holub所寫(xiě)的《Compiler Design in C》一書(shū)的附隨軟件，其中有作者自己編寫(xiě)的詞法分析和語(yǔ)法分析工具LeX，occs和LLama，該軟件包還包括一個(gè)顯示C語(yǔ)言分析過(guò)程的程序
標(biāo)簽： I. Compiler Design Allen
上傳時(shí)間： 2014-01-08
上傳用戶(hù)：siguazgb
Hopfield Model Autoassociative Memory 源碼, 經(jīng)典的HOPFIELD人工神經(jīng)網(wǎng)絡(luò)例子源碼
標(biāo)簽： Autoassociative Hopfield HOPFIELD Memory
上傳時(shí)間： 2015-01-05
上傳用戶(hù)：皇族傳媒
Bidirectional Associative Memory Heteroassociative Memory 人工智能人工神經(jīng)網(wǎng)絡(luò)源碼;
標(biāo)簽： Memory Heteroassociative Bidirectional Associative
上傳時(shí)間： 2015-01-05
上傳用戶(hù)：372825274
PGP Components使用PGP算法的加密控件。(有源代碼）工作在：D2 D3 D4 D5。作者：Michael in der Wiesche
標(biāo)簽： Components PGP Michael Wiesche
上傳時(shí)間： 2013-12-28
上傳用戶(hù)：koulian
提供字符串、文件 及 Memory Streams 加密/解密的控件 ( 2.1 版，附原始程序代碼 )，作者 : Konstantin Borodachev。
標(biāo)簽： Streams Memory 2.1 字符串
上傳時(shí)間： 2013-12-28
上傳用戶(hù)：stvnash
a set of cross-platform tools that is useful for programming the GBA written in Java.
標(biāo)簽： cross-platform programming written useful
上傳時(shí)間： 2015-01-06
上傳用戶(hù)：yd19890720
This book introduces embedded systems to C and C++ programmers. Topics include testing memory devices, writing and erasing Flash memory, verifying nonvolatile memory contents, controlling on-chip peripherals, device driver design and implementation, optimizing embedded code for size and speed, and making the most of C++ without a performance penalty. Pages : 336 Slots : 1
標(biāo)簽： programmers introduces embedded include
上傳時(shí)間： 2013-12-10
上傳用戶(hù)：shizhanincc
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