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The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device INCLUDEs an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽：
MULTICHANNEL
5.5
TO
RS
上傳時間：
2013-10-19
上傳用戶：ddddddd
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UART測試程序-AT91SAM9260://* The software is delivered "AS IS" without warranty or condition of any//* kind, either express, implied or statutory. This INCLUDEs without//* limitation any warranty or condition with respect to merchantability or//* fitness for any particular purpose, or against the infringements of//* intellectual property rights of others.
標(biāo)簽：
UART
9260
SAM
AT
上傳時間：
2013-11-18
上傳用戶：yepeng139
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This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also INCLUDEs a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
標(biāo)簽：
routines
driver
P90
301
上傳時間：
2013-11-23
上傳用戶：weixiao99
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The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note INCLUDEs a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
標(biāo)簽：
routines
slave
I2C
87L
上傳時間：
2013-11-19
上傳用戶：shirleyYim
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The 87C576 INCLUDEs two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
標(biāo)簽：
87C576
微控制器
編程
上傳時間：
2013-10-21
上傳用戶：xiaozhiqban
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基于ADSP-BF561的數(shù)字?jǐn)z像系統(tǒng)設(shè)計Design of Digital Video Camera System Based on Digital Signal ProcessorADSP-BF561（浙江大學(xué) 信息與通信工程研究所，浙江 杭州 310027） 馬海杰, 劉云海摘要：介紹了基于ADI雙核的數(shù)字信號處理芯片ADSP-BF561 的數(shù)字?jǐn)z像系統(tǒng)實現(xiàn)方案。系統(tǒng)包括硬件和軟件兩部分，硬件主要有ADSP-BF561及其外圍電路、音視頻模數(shù)/數(shù)模轉(zhuǎn)換、CF卡/微硬盤接口等部分。軟件主要有操作系統(tǒng)及音視頻編解碼算法等部分。關(guān)鍵詞：ADSP-BF561 ;數(shù)字?jǐn)z像機;微硬盤;MPEG-4;A/D;D/A中圖分類號:TN948.41文獻標(biāo)識碼:AAbstract: An implementation of digital video camera system based on ADI dual core digital signal processor ADSP-BF561 is introduced. The system can be divided into two parts——hardware and software design. The hardware design INCLUDEs ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software INCLUDEs operating system , audio and video coding algorithm.Key words: ADSP-BF561; digital video camera; microdrive; MPEG-4;A/D;D/A
標(biāo)簽：
ADSP-BF
561
數(shù)字?jǐn)z像
系統(tǒng)設(shè)計
上傳時間：
2013-11-10
上傳用戶：yl1140vista
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The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function
Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper INCLUDEs example design, testbench; and both implementation and simulation scripts
標(biāo)簽：
Transceiver
Virtex
Wizar
GTP
上傳時間：
2013-10-23
上傳用戶：leyesome
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ref-sdr-sdram-vhdl代碼
SDR SDRAM Controller v1.1 readme.txt
This readme file for the SDR SDRAM Controller INCLUDEs information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture.
Last updated September, 2002
Copyright ?2002 Altera Corporation. All rights reserved.
標(biāo)簽：
sdram
vhdl
ref
sdr
上傳時間：
2013-11-13
上傳用戶：takako_yang
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Abstract: The 1-Wire product family INCLUDEs numerous devices that can be easily evaluated using a Windows®-based
標(biāo)簽：
Wire
評估套件
上傳時間：
2013-10-12
上傳用戶：fudong911
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Abstract: This application note helps system designers choose the correct external components for use with the MAX16948 dualremote antenna LDO/switch, thus ensuring that automobile-regulated phantom antenna supply and output-current-monitoring circuitrymeet performance objectives. An electronic calculator is provided that helps specify the critical external components for theMAX16948, thus reducing design time. The calculator also determines the device's analog output voltage, output current-limitthreshold, and output current-sensing accuracies. The calculator INCLUDEs new automatic Step By Step feature that assists designerswith component choice. To use the new automatic feature, click on the Step By Step button relative to the desired section.
標(biāo)簽：
16948
MAX
LDO
遙控天線
上傳時間：
2013-11-04
上傳用戶：lhll918
