·詳細(xì)說明：學(xué)習(xí)USB2.0驅(qū)動(dòng)程序設(shè)計(jì)源碼，包括Windows DDK Driver驅(qū)動(dòng)的詳細(xì)設(shè)計(jì)，U盤，MP3的程序設(shè)計(jì)例子- Studies the USB2.0 driver design source code, INCLUDING Windows DDK Driver actuation detailed design, U plate, MP3 programming example
標(biāo)簽： USB 2.0 驅(qū)動(dòng) 程序設(shè)計(jì)
上傳時(shí)間： 2013-06-04
上傳用戶：宋桃子
本文論述了狀態(tài)機(jī)的verilog編碼風(fēng)格,以及不同編碼風(fēng)格的優(yōu)缺點(diǎn)，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design INCLUDING coding style approaches and a few additional tricks.
標(biāo)簽： Synthesis Machine Coding Styles
上傳時(shí)間： 2013-10-15
上傳用戶：dancnc
Abstract: What can be simpler than designing with CMOS and BiCMOS? These technologies are very easy to use butthey still require careful design. This tutorial discusses the odd case of circuits that seem to work but exhibit somepeculiar behaviors—INCLUDING burning the designer's fingers!
上傳時(shí)間： 2013-11-03
上傳用戶：dick_sh
Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),INCLUDING the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of device resources forpower management, I²C communication circuit configurations, and I²C characteristics relative to device power-up sequences andinitializations. Additional discussions on decoupling are provided to support developing strategies for mitigating power-supply pushingof device frequency.
標(biāo)簽： I2C 高精度 實(shí)時(shí)時(shí)鐘
上傳時(shí)間： 2013-11-23
上傳用戶：WMC_geophy
Abstract: A laser module designer can use a fixed resistor, mechanical pot, digital pot, or a digital-to-analogconverter (DAC) to control the laser driver's modulation and bias currents. The advantages of a programmablemethod (POT or DAC) are that the manufacturing process can be automated and digital control can be applied(e.g., to compensate for temperature). Using POTs can be a more simple approach than a DAC. There can be aslight cost advantage to using a POT, but this is usually not significant relative to other pieces of the design.Using a DAC can offer advantages, INCLUDING improved linearity (translating to ease of software implementationand ability to hit the required accuracy), increased board density, a wider range of resolutions, a betteroptimization range, ease of use with a negative voltage laser driver, and unit-to-unit consistency
標(biāo)簽： POT DAC 應(yīng)用筆記 校準(zhǔn)
上傳時(shí)間： 2013-11-13
上傳用戶：ca05991270
This application note is an overview discussion of theLinear Technology SPICE macromodel library. It assumeslittle if any prior knowledge of this software library or itshistory. However, it does assume familiarity with both theanalog simulation program SPICE (or one of its manyderivatives), and modern day op amps, INCLUDING bipolar,JFET, and MOSFET amplifier technologies
標(biāo)簽： LTC 運(yùn)算放大器 模型
上傳時(shí)間： 2013-11-14
上傳用戶：zhanditian
Application considerations and circuits for the LT1001 and LT1002 single and dual precision amplifiers are illustrated in a number of circuits, INCLUDING strain gauge signal conditioners, linearized platinum RTD circuits, an ultra precision dead zone circuit for motor servos and other examples.
標(biāo)簽： 精密 運(yùn)算放大器
上傳時(shí)間： 2013-10-18
上傳用戶：dreamboy36
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, INCLUDING any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標(biāo)簽： Architecture ExpressTM PCI
上傳時(shí)間： 2013-11-03
上傳用戶：gy592333
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect INCLUDING design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
This product integration guide provides application circuit information for theSmartMesh® LTP5903PC wireless embedded network manager. This guide is acompanion to the 020-0039 SmartMesh LTP5903PC Datasheet, whichdescribes overall product behavior, INCLUDING detailed information about normaloperating conditions, electrical and mechanical specifications, hardware andsoftware interfaces, and connector pinouts.
標(biāo)簽： Integration Hardware Guide 5903
上傳時(shí)間： 2013-11-14
上傳用戶：農(nóng)藥鋒6
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