The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the INTERNAL PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
SL811開發資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with INTERNAL full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. INTERNALly,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
The ability to create groups of reports, and grant users access to reports by group. The ability to generate reports as PDF, XLS, HTML, and CSV files. The ability to generate bar, pie and xy charts for inclusion in reports. The ability to schedule and email PDF, XLS, and CSV reports. The ability to define reusable report parameters. Available parameter types include Date, Text, and Query Parameters. The ability to create multiple DataSources for use in generating reports. Support for JNDI DataSources and INTERNAL connection pooling via Commons-DBCP is included. The ability to upload and hot deploy new reports. Web based administration of users, groups, reports, parameters, and datasources. Cross platform database support via Hibernate based persistence layer. Available in a preconfigured bundle with Apache Tomcat.
This program prints the C8051F124 die temperature out the hardware UART at 115200bps. This example uses the INTERNAL 24.5MHz oscillator multiplied by 2 using the on-chip PLL (SYSCLK = 49MHz).
This a very simple Yee algorithm 3D FDTD code in C implementing the free space form of Maxwell s equations on a Cartesian grid. There are no INTERNAL materials or geometry. The code as delivered simulates an idealized rectangular waveguide by treating the interior of the mesh as free space/air and enforcing PEC (Perfect Electric Conductor) conditions on the faces of the mesh.
These routines transmit and receive serial data using two general
* I/O pins, in 8 bit, No parity, 1 stop bit format. They are useful
* for performing serial I/O on 8051 derivatives not having an
* INTERNAL UART, or for implementing a second serial channel.
8051 monitor programm:
- use external ram to run user program
- use eeprom to save user program
- provide single step debug,
can read INTERNAL register and ram
