fet440_wdt_02.s43 - WDT, Toggle P5.1, Interval Overflow ISR, 32kHz ACLK
標(biāo)簽： Interval Overflow Toggle ACLK
上傳時(shí)間： 2015-11-26
上傳用戶：lijinchuan
nRF24L01_EVB子程序－ISR,定義中斷方式
上傳時(shí)間： 2013-12-31
上傳用戶：qq521
include:alarm, DMA, fine_gainde flash, HighResTime,ISR,Simple flash,and so on
標(biāo)簽： flash HighResTime fine_gainde include
上傳時(shí)間： 2016-08-12
上傳用戶：wpwpwlxwlx
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and used only durring TA_ISR. ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
標(biāo)簽： Toggle Description 5.1 Contmode
上傳時(shí)間： 2014-01-04
上傳用戶：gut1234567
Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/38400 = ~27.31 (01Bh|03h) // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & XOUT is required for ACLK
標(biāo)簽： character interrupt received triggers
上傳時(shí)間： 2016-10-31
上傳用戶：rishian
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時(shí)間： 2013-11-11
上傳用戶：gundamwzc
這是一個(gè)標(biāo)準(zhǔn)的s3c44b0x向量中斷程序，程序的注釋行詳細(xì)介紹了，向量中斷方式下，處理器是如何找到ISR的
標(biāo)簽： s3c44b0x 標(biāo)準(zhǔn) 向量中斷 程序
上傳時(shí)間： 2014-08-21
上傳用戶：caozhizhi
This code implements the basic functions for an I2C slave device using the SSP module. All I2C functions are handled in an ISR. Bytes written to the slave are stored in a buffer. After a number of bytes have been written, the master device can then read the bytes back from the buffer.
標(biāo)簽： implements I2C functions the
上傳時(shí)間： 2015-04-02
上傳用戶：邶刖
USB51S庫一共有3個(gè)文件，包括USB51S.LIB，ISR.C，ISR.H（為了增加USB通信的靈活性，并沒有把所有的子程序都封裝倒USB51S.LIB，而是在ISR.C建立部分通信程序，這樣方便用戶修改
上傳時(shí)間： 2014-01-18
上傳用戶：hustfanenze
請(qǐng)把uCosII的文件放到Core文件夾下。 共有三個(gè)任務(wù)，A，B為定時(shí)調(diào)度。C通過鍵盤的ISR中發(fā)送消息到郵箱。 程序在優(yōu)龍開發(fā)板上調(diào)試通過，用的uCosII是2.70版本。
上傳時(shí)間： 2015-06-14
上傳用戶：jjj0202
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