The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標(biāo)簽：
system-on-chip
integrated
designed
reusable
上傳時(shí)間：
2013-12-20
上傳用戶(hù)：小眼睛LSL
