Jitter is extremely important in systems using PLL-based
clock drivers. The effects of Jitter range from not having any
effect on system operation to rendering the system completely
non-functional. This application note provides the reader
with a clear understanding of Jitter in high-speed systems. It
introduces the reader to various kinds of Jitter in high-speed
systems, their causes and their effects, and methods of reducing
Jitter. This application note will concentrate on Jitter in PLL-based frequency synthesizers.
Abstract: This application note describes how sampling clock Jitter (time interval error or "TIE Jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) Jitter tolerance in these devices. The article also provides an application example ofa simple highly Jittered cycle-skipped sampling clock and describes a method for generating a properbroadband Jittered clock. The document then goes on to compare Maxim's audio DAC Jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high Jitter tolerance allows very simple and low-cost sampleclock implementations.
Highlights the LTC1062 as a lowpass filter in a phase lock loop. Describes how the loop's bandwidth can be increased and the VCO output Jitter reduced when the LTC1062 is the loop filter. Compares it with a passive RC loop filter. Also discussed is the use of LTC1062 as simple bandpass and bandstop filter.
