The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions LIKE described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時間： 2013-10-24
上傳用戶：s藍莓汁
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-LIKE system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes LIKE
上傳時間： 2013-11-08
上傳用戶：immanuel2006
We would LIKE to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
上傳時間： 2015-01-02
上傳用戶：zhangyi99104144
Modern electronic systems solve so many difficult problems that they often seem LIKE magic. Nonetheless, these systems all have thesame basic limitation: they need a source of electrical power! Most of the time this is a straightforward challenge for the electronicdesigner, because there are many power-delivery solutions. Yet sometimes a device has no direct power source, and running wiresor replacing batteries is impractical. Even when long-life batteries are usable, they eventually need to be replaced, which requires aservice call.
標簽： 能量收集
上傳時間： 2015-01-03
上傳用戶：zukfu
Giga Crime Fighting Mecha Gelato-Bots: The Supreme Icecream-Tron Revolution 8,000,000. A top-down adventure game with three themes; mecha, anime and icecream. This project hopes to evolve with action/rpg/multiplayer elements LIKE classic console games.
標簽： Icecream-Tron Gelato-Bots Revolution 000
上傳時間： 2013-12-18
上傳用戶：D&L37
Grammatica is a C# and Java parser generator (compiler compiler). It improves upon simlar tools (LIKE yacc and ANTLR) by creating well-commented and readable source code, by having automatic error recovery and detailed error messages, and by support for testing and debugging grammars without generating source code. It supports LL(k) grammars with an unlimited number of look-ahead tokens.
標簽： compiler Grammatica generator improves
上傳時間： 2015-01-11
上傳用戶：stella2015
title=Windows NT/2000/XP 一個RAM-DISK文件系統驅動 memo=SwapFs is a driver for Windows NT/2000/XP that let you use a Linux swap partition for temporary storage, LIKE a RAM-disk. It is possible to put Windows page file on it. It is implemented as a disk filter driver.
標簽： Windows 2000 RAM-DISK SwapFs
上傳時間： 2015-02-04
上傳用戶：ljmwh2000
title=Windows NT/2000/XP 一個RAM-DISK文件系統驅動 memo=SwapFs is a driver for Windows NT/2000/XP that let you use a Linux swap partition for temporary storage, LIKE a RAM-disk. It is possible to put Windows page file on it. It is implemented as a disk filter driver.
標簽： Windows 2000 RAM-DISK SwapFs
上傳時間： 2014-01-25
上傳用戶：sdq_123
This matrix C++ template class library is for performing common matrix operations in your C++ program LIKE any other built-in data types. To install the package, just copy MATRIX.H file into the INCLUDE directory of your compiler and include this header file in your program source file
標簽： matrix performing operations template
上傳時間： 2013-12-21
上傳用戶：wys0120
