Avalanche photodiodes (APDs) are widely utilized in laserbased fiberoptic systems to convert optical data intoelectrical form. The APD is usually packaged with a signalconditioning amplifier in a small module. An APD receivermodule and attendant circuitry appears in Figure 1. TheAPD module (figure right) contains the APD and a transimpedance(e.g., current-to-voltage) amplifier. An opticalport permits interfacing fiberoptic cable to the APD’sphotosensitive portion. The module’s compact constructionfacilitates a direct, low loss connection between theAPD and the amplifier, necessary because of the extremelyhigh speed data rates involved
上傳時間： 2013-10-25
上傳用戶：brain kung
The LTM4600 DC/DC μModule regulator is a complete highpower density stepdown regulator for 10A continuous (14Apeak) loads. The device has two voltage options: 20VINmaximum for the LTM4600EV and 28VIN maximum for theLTM4600HVEV each housed in a small 15mm ¥ 15mm ¥2.8mm LGA surface mount package.
上傳時間： 2013-10-10
上傳用戶：adada
The latest generation of Texas Instruments (TI) boardmountedpower modules utilizes a pin interconnect technologythat improves surface-mount manufacturability.These modules are produced as a double-sided surfacemount(DSSMT) subassembly, yielding a case-less constructionwith subcomponents located on both sides of theprinted circuit board (PCB). Products produced in theDSSMT outline use the latest high-efficiency topologiesand magnetic-component packaging. This providescustomers with a high-efficiency, ready-to-use switchingpower module in a compact, space-saving package. Bothnonisolated point-of-load (POL) switching regulators andthe isolated dc/dc converter modules are being producedin the DSSMT outline.TI’s plug-in power product line offers power modules inboth through-hole and surface-mount packages. The surfacemountmodules produced in the DSSMT outline use asolid copper interconnect with an integral solder ball fortheir
上傳時間： 2013-10-10
上傳用戶：1184599859
/*--------- 8051內核特殊功能寄存器 -------------*/ sfr ACC = 0xE0; //累加器 sfr B = 0xF0; //B 寄存器 sfr PSW = 0xD0; //程序狀態字寄存器 sbit CY = PSW^7; //進位標志位 sbit AC = PSW^6; //輔助進位標志位 sbit F0 = PSW^5; //用戶標志位0 sbit RS1 = PSW^4; //工作寄存器組選擇控制位 sbit RS0 = PSW^3; //工作寄存器組選擇控制位 sbit OV = PSW^2; //溢出標志位 sbit F1 = PSW^1; //用戶標志位1 sbit P = PSW^0; //奇偶標志位 sfr SP = 0x81; //堆棧指針寄存器 sfr DPL = 0x82; //數據指針0低字節 sfr DPH = 0x83; //數據指針0高字節 /*------------ 系統管理特殊功能寄存器 -------------*/ sfr PCON = 0x87; //電源控制寄存器 sfr AUXR = 0x8E; //輔助寄存器 sfr AUXR1 = 0xA2; //輔助寄存器1 sfr WAKE_CLKO = 0x8F; //時鐘輸出和喚醒控制寄存器 sfr CLK_DIV = 0x97; //時鐘分頻控制寄存器 sfr BUS_SPEED = 0xA1; //總線速度控制寄存器 /*----------- 中斷控制特殊功能寄存器 --------------*/ sfr IE = 0xA8; //中斷允許寄存器 sbit EA = IE^7; //總中斷允許位 sbit ELVD = IE^6; //低電壓檢測中斷控制位 8051
上傳時間： 2013-10-30
上傳用戶：yxgi5
為了使音頻信號分析儀小巧可靠，成本低廉，設計了以2片MSP430F1611單片機為核心的系統。該系統將音頻信號送入八階巴特沃茲低通濾波器，對信號進行限幅放大、衰減、電平位移、緩沖，并利用一單片機負責對前級處理后的模擬信號進行采樣，將采集得到的音頻信號進行4 096點基2的FFT計算，并對信號加窗函數提高分辨率，另一單片機負責對信號的分析及控制顯示設備。此設計精確的測量了音頻信號的功率譜、周期性、失真度指標，達到較高的頻率分辨率，并能將測量結果通過紅外遙控器顯示在液晶屏上。 Abstract: o make the audio signal analyzer cheaper， smaller and more reliable， this system sends the audio signal to the eight-order butterworth filter， and then amplifies， attenuates， buffers it in a limiting range， transfers the voltage level of the signal before utilizing two MSP430F1611 MCU to realize the audio analysis. One is charged for sampling and dealing with the processed audio signal collected by the 4096 point radix-2 FFT calculation and imposes the window function to improve the frequency resolution. The other one controls the display and realizes the spectrum， periodicity， power distortion analysis in high resolution which is displayed in the LCD screen through the infrared remote control.
上傳時間： 2013-12-11
上傳用戶：jasonheung
提出了一種以S3C2440A為核心處理器的銀行評價器的設計方案，并結合XILINX公司的XL95144XL型CPLD，輔助S3C2440A，實現該銀行評價器的各部分功能以及系統信號之間的相互協調。該評價器在系統設計上采用液晶屏顯示，代替了以往簡單的數碼管電路的顯示模式，在視覺上給人以全新的享受。同時，評價器增加了新的網絡供電方式，只要將評價器連接上網絡就可以正常工作，方便了客戶的使用。總之，此款銀行評價器采用了嵌入式系統的設計方案，大大豐富了系統功能，實現一個銀行評價器設計的新突破。 Abstract: S3C2440A of SamSung company is the core component of the embedded system. A design of bank assessor based on S3C2440A was provided in this paper. It used XL95144XL combined with S3C2440A to realize all the functions and coordination with system signals. This bank assessor used LCD to display instead of the former simple digital display and provided a new seusuous enjoment. Meanwhile，it provided a new method of network power supply，that the bank assessor could regularly work once it connected to the network，which is convenient for customers to use. In a word，this assessor takes embedded system，enriches the system’s functions and reclizes a new breakout.
標簽： S3C2440A
上傳時間： 2013-11-03
上傳用戶：taa123456
Mega16是一款采用先進RISC精簡指令，內置A/D的8位單片機，可支持低電壓聯機 Flash和EEPROM 寫入功能；同時還支持 Basic和C 等高級語言編程。用它設計電子時鐘不僅成本低，硬件簡單，而且很容易實現系統移植。介紹了如何利用AVR系列單片機Mega16及1602字符液晶來設計電子時鐘的方法，同時給出了相應的電路原理及部分語言程序。 Abstract: ?Mega16 is a high-performance, low power consumption, the use of advanced RISC concise instructions, built-in A/D 8-bit microcontrollers, the on-line support for low-voltage Flash, EEPROM write function. Except Mega16 also support the Basic, C, and other high-level language programming.The electronic clock which is deisgned by Mega16 is not only low-cost, simple hardware, but easy to achieve system migration.The design method of electrioic clock based on the AVR Mega16 and character LCD1602 is introduced in this paper,and the corresponding circuit electrionic and some language program are given.
上傳時間： 2014-12-27
上傳用戶：zl5712176
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上傳時間： 2013-10-13
上傳用戶：bakdesec
The P82B715 I2C Buffer was designed toextend the range of the local I2C bus out to50 Meters. This application note describesthe results of testing the buffer on severaldifferent types of cables to determine themaximum operating distances possible. Theresults are summarized in a table for easyreference.
標簽： extender P82B715 Using I2C
上傳時間： 2014-12-28
上傳用戶：lou45566
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上傳時間： 2013-11-19
上傳用戶：shirleyYim
