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鎖定放大是微弱信號檢測的重要手段。基于相關(guān)檢測理論，利用開關(guān)電容的開關(guān)實現(xiàn)鎖定放大器中乘法器的功能，提出開關(guān)電容和積分器相結(jié)合以實現(xiàn)相關(guān)檢測的方法，并設(shè)計出一種鎖定放大器。該鎖定放大器將微弱信號轉(zhuǎn)化為與之相關(guān)的方波，通過后續(xù)電路得到正比于被測信號的直流電平，為后續(xù)采集處理提供方便。測量數(shù)據(jù)表明鎖定放大器前級可將10-6 A的電流轉(zhuǎn)換為10-1 V的電壓，后級通過帶通濾波器級聯(lián)可將信號放大1×105倍。該方法在降低噪聲的同時，可對微弱信號進行放大，線性度較高、穩(wěn)定性較好。
Abstract:
Lock-in Amplifying（LIA）is one of important means for weak signal detection. Based on cross-correlation detection theory， switch in the swithched capacitor was used as multiplier of LIA， and a new method of correlation detection was proposed combining swithched capacitor with integrator. A kind of LIA was designed which can convert the weak signal to square-wave， then DC proportional to measured signal was obtained through follow-up conditioning circuit， providing convenience for signal acquisition and processing. The measured data shows that the electric current（10-6 A） can be changed into voltage（10-1 V） by LIA， and the signal is magnified 1×105 times by cascade band-pass filter. The noise is suppressed and the weak signal is amplified. It has the advantages of good linearity and stability.
標(biāo)簽：
開關(guān)電容
鎖定放大器
上傳時間：
2013-11-29
上傳用戶：黑漆漆
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摘要
本研究計劃之目的，在整合應(yīng)用以ARM為基礎(chǔ)的嵌入式多媒體實時操作系統(tǒng)于H.264/MPEG-4多媒體上。由于H.264是一種因應(yīng)實時系統(tǒng)(RTOS)所設(shè)計的可擴展性串流傳輸(scalability stream media communication)的編碼技術(shù)。H.264主要架構(gòu)于細(xì)細(xì)粒可擴展(Fine Granula Scalability,FGS)的壓縮編碼機制。細(xì)粒度可擴展壓縮編碼技術(shù)是最新MPEG-4串流式傳輸標(biāo)準(zhǔn)，能依頻寛的差異來調(diào)整傳輸?shù)姆绞健＜?xì)粒度擴展縮編碼技術(shù)以編入可選擇性的增強層(enhanced layers)于碼中，來提高影像傳輸?shù)馁|(zhì)量。本計劃主要在于設(shè)計一種簡單有效的實時階層可擴展的影像傳輸系統(tǒng)。在增強層編碼及H.264的基本層(base layer)編碼上使用漸進的細(xì)粒度可擴展編碼(Progressive Fine Granularity Scalable,PFGS)能直接使用H.264的格式特色來實現(xiàn)FGS。同時加入了LB-LLF(Layer-Based Least-Laxity-Fir stscheduling algorithm)的排程算法，來增
進網(wǎng)路傳輸影像的質(zhì)量。由實驗結(jié)果顯示本系統(tǒng)在串流影像質(zhì)量PSNR值上確有較佳的效能。
標(biāo)簽：
芯片系統(tǒng)
架構(gòu)
開發(fā)平臺
上傳時間：
2014-12-26
上傳用戶：mpquest
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Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
標(biāo)簽：
Xilinx
FPGA
DC
輸出
上傳時間：
2013-10-22
上傳用戶：liu999666
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在現(xiàn)代通信系統(tǒng)中，電話語音的頻帶被限制在300 Hz～4 kHz的范圍內(nèi)，帶來了語音可懂度和自然度的降低。為了在不增加額外成本的前提下提高語音的可懂度和自然度，進行了電話語音頻帶擴展的研究。提出了一種改進的基于碼本映射的語音帶寬擴展算法：在碼本映射的過程中，使用加權(quán)系數(shù)來得到映射碼本。客觀測試結(jié)果表明，用此算法得到的寬帶語音的譜失真度比用一般的碼本映射降低至少2%。主觀測試結(jié)果表明，用此算法得到的寬帶語音具有更好的可懂度和自然度。
Abstract:
In modern communication systems， the bandwidth of telephone speech is limited from 300Hz to 4 kHz， which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness， without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping， weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%， comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.
標(biāo)簽：
映射
帶寬
擴展
語音
上傳時間：
2014-12-29
上傳用戶：15501536189
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6小時學(xué)會labview,
labview Six Hour Course – Instructor Notes
This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are:
Instructor Notes.doc – this document.
labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course.
Convert C to F (Ex1).vi – Exercise 1 solution VI.
Convert C to F (Ex2).vi – Exercise 2 solution subVI.
Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI.
Temperature Monitor (Ex3).vi – Exercise 3 solution VI.
Thermometer (Ex4).vi – Exercise 4 solution subVI.
Convert C to F (Ex4).vi – Exercise 4 solution subVI.
Temperature Logger (Ex4).vi – Exercise 4 solution VI.
Multiplot Graph (Ex5).vi – Exercise 5 solution VI.
Square Root (Ex6).vi – Exercise 6 solution VI.
State Machine 1 (Ex7).vi – Exercise 7 solution VI.
The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標(biāo)簽：
labview
上傳時間：
2013-10-13
上傳用戶：zjwangyichao
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PCB線寬和電流關(guān)系公式
先計算Track的截面積，大部分PCB的銅箔厚度為35um（即 1oz）它乘上線寬就是截面積，注意換算成平方毫米。 有一個電流密度經(jīng)驗值，為15~25安培/平方毫米。把它稱上截面積就得到通流容量。
I=KT（0.44）A（0.75）， 括號里面是指數(shù)，
K為修正系數(shù)，一般覆銅線在內(nèi)層時取0.024，在外層時取0.048
T為最大溫升，單位為攝氏度（銅的熔點是1060℃）
A為覆銅截面積，單位為square mil.
I為容許的最大電流，單位為安培。
一般 10mil=0.010inch=0.254mm 1A ， 250mil=6.35mm 8.3A ？倍數(shù)關(guān)系，與公式不符 ？
標(biāo)簽：
PCB
寬
電流
上傳時間：
2013-11-12
上傳用戶：ljd123456
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Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
標(biāo)簽：
Xilinx
FPGA
DC
輸出
上傳時間：
2013-10-22
上傳用戶：aeiouetla
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21天學(xué)會用JAVA開發(fā)網(wǎng)絡(luò)游戲
書籍語言： 簡體中文
書籍類型： 程序設(shè)計
授權(quán)方式： 免費軟件
書籍大小： 287 KB
書籍等級：
整理時間： 2004-11-3 20:41:10
With all of the media attention that is focused on the Internet and the World Wide Web, figuring out exactly what they are all about is sometimes difficult. Are they just a neat new way to market products or will they truly offer us a new medium of communication that will someday surpass even televisions and telephones? The answer is, who knows? Unfortunately, the ultimate use for the Internet is still unknown. This is because it is still in such a state of flux that it s pretty much impossible to accurately predict where it will end up. However, you can look at the evidence of what is there now and gain some insight into what the Internet might become, at least in terms of games.
標(biāo)簽：
書籍
JAVA
2004
287
上傳時間：
2013-12-20
上傳用戶：天誠24
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This project is created using the Keil ARM CA Compiler.
The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1
This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series.
You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標(biāo)簽：
the
Analyzer
Compiler
project
上傳時間：
2013-12-19
上傳用戶：Yukiseop
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物流分析工具包。Facility location: Continuous minisum facility location, alternate location-allocation (ALA) procedure, discrete uncapacitated facility location
Vehicle routing: VRP, VRP with time windows, traveling salesman problem (TSP)
Networks: Shortest path, min cost network flow, minimum spanning tree problems
Geocoding: U.S. city or ZIP code to longitude and latitude, longitude and latitude to nearest city, Mercator projection plotting
Layout: Steepest descent pairwise interchange (SDPI) heuristic for QAP
Material handling: Equipment selection
General purpose: Linear programming using the revised simplex method, mixed-integer linear programming (MILP) branch and bound procedure
Data: U.S. cities with populations of at least 10,000, U.S. highway network (Oak Ridge National Highway Network), U.S. 3- and 5-digit ZIP codes
標(biāo)簽：
location
location-allocation
Continuous
alternate
上傳時間：
2015-05-17
上傳用戶：kikye
