高速數(shù)字系統(tǒng)設(shè)計(jì)下載pdf:High-Speed Digital SystemDesign—A Handbook ofInterconnect Theory and DesignPracticesStephen H. HallGarrett W. HallJames A. McCallA Wiley-Interscience Publication JOHN WILEY & SONS, INC.New York • Chichester • Weinheim • Brisbane • Singapore • TorontoCopyright © 2000 by John Wiley & Sons, Inc.speeddigital systems at the platform level. The book walks the reader through everyrequired concept, from basic transmission line theory to digital timing analysis, high-speedmeasurement techniques, as well as many other topics. In doing so, a unique balancebetween theory and practical applications is achieved that will allow the reader not only tounderstand the nature of the problem, but also provide practical guidance to the solution.The level of theoretical understanding is such that the reader will be equipped to see beyondthe immediate practical application and solve problems not contained within these pages.Much of the information in this book has not been needed in past digital designs but isabsolutely necessary today. Most of the information covered here is not covered in standardcollege curricula, at least not in its focus on digital design, which is arguably one of the mostsignificant industries in electrical engineering.The focus of this book is on the design of robust high-volume, high-speed digital productssuch as computer systems, with particular attention paid to computer busses. However, thetheory presented is applicable to any high-speed digital system. All of the techniquescovered in this book have been applied in industry to actual digital products that have beensuccessfully produced and sold in high volume.Practicing engineers and graduate and undergraduate students who have completed basicelectromagnetic or microwave design classes are equipped to fully comprehend the theorypresented in this book. At a practical level, however, basic circuit theory is all thebackground required to apply the formulas in this book.
標(biāo)簽： 高速數(shù)字 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-10-26
上傳用戶：縹緲
Video cable driver amplifi er output stages traditionallyrequire a supply voltage of at least 6V in order to providethe required output swing. This requirement is usuallymet with 5V supplies by adding a boost regulator or asmall local negative rail, say via the popular LT®1983-3.Such additional circuitry is unnecessary in typical 1VP-Pvideo connections, such as HD component video, if thecable driver amplifi ers simply offer near rail-to-rail outputcapability when powered from 5V.
上傳時(shí)間： 2013-11-16
上傳用戶：yanyangtian
Abstract: As electronic systems take over many of the mechanical functions in a car—ranging from engine timing to steering andbraking—there is a growing concern about fault tolerance. There should not be a single point of failure that would prevent a car fromat least "limping" off the road or making it to the nearest service station. Redundant systems, watchdog timers, and other controlcircuits are used to reroute signals and perform other functions that ensure that a vehicle can safely make it off the road when afailure occurs.
標(biāo)簽： 看門狗定時(shí)器 汽車安全系統(tǒng)
上傳時(shí)間： 2013-11-10
上傳用戶：diets
摘要 本研究計(jì)劃之目的，在整合應(yīng)用以ARM為基礎(chǔ)的嵌入式多媒體實(shí)時(shí)操作系統(tǒng)于H.264/MPEG-4多媒體上。由于H.264是一種因應(yīng)實(shí)時(shí)系統(tǒng)(RTOS)所設(shè)計(jì)的可擴(kuò)展性串流傳輸(scalability stream media communication)的編碼技術(shù)。H.264主要架構(gòu)于細(xì)細(xì)?？蓴U(kuò)展(Fine Granula Scalability,FGS)的壓縮編碼機(jī)制。細(xì)粒度可擴(kuò)展壓縮編碼技術(shù)是最新MPEG-4串流式傳輸標(biāo)準(zhǔn)，能依頻寛的差異來(lái)調(diào)整傳輸?shù)姆绞健＜?xì)粒度擴(kuò)展縮編碼技術(shù)以編入可選擇性的增強(qiáng)層(enhanced layers)于碼中，來(lái)提高影像傳輸?shù)馁|(zhì)量。本計(jì)劃主要在于設(shè)計(jì)一種簡(jiǎn)單有效的實(shí)時(shí)階層可擴(kuò)展的影像傳輸系統(tǒng)。在增強(qiáng)層編碼及H.264的基本層(base layer)編碼上使用漸進(jìn)的細(xì)粒度可擴(kuò)展編碼(Progressive Fine Granularity Scalable,PFGS)能直接使用H.264的格式特色來(lái)實(shí)現(xiàn)FGS。同時(shí)加入了LB-LLF(Layer-Based Least-Laxity-Fir stscheduling algorithm)的排程算法，來(lái)增 進(jìn)網(wǎng)路傳輸影像的質(zhì)量。由實(shí)驗(yàn)結(jié)果顯示本系統(tǒng)在串流影像質(zhì)量PSNR值上確有較佳的效能。
標(biāo)簽： 芯片系統(tǒng) 架構(gòu) 開發(fā)平臺(tái)
上傳時(shí)間： 2014-12-26
上傳用戶：mpquest
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時(shí)間： 2013-10-22
上傳用戶：liu999666
在現(xiàn)代通信系統(tǒng)中，電話語(yǔ)音的頻帶被限制在300 Hz～4 kHz的范圍內(nèi)，帶來(lái)了語(yǔ)音可懂度和自然度的降低。為了在不增加額外成本的前提下提高語(yǔ)音的可懂度和自然度，進(jìn)行了電話語(yǔ)音頻帶擴(kuò)展的研究。提出了一種改進(jìn)的基于碼本映射的語(yǔ)音帶寬擴(kuò)展算法：在碼本映射的過(guò)程中，使用加權(quán)系數(shù)來(lái)得到映射碼本。客觀測(cè)試結(jié)果表明，用此算法得到的寬帶語(yǔ)音的譜失真度比用一般的碼本映射降低至少2%。主觀測(cè)試結(jié)果表明，用此算法得到的寬帶語(yǔ)音具有更好的可懂度和自然度。 Abstract: In modern communication systems， the bandwidth of telephone speech is limited from 300Hz to 4 kHz， which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness， without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping， weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%， comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.
標(biāo)簽： 映射 帶寬 擴(kuò)展 語(yǔ)音
上傳時(shí)間： 2014-12-29
上傳用戶：15501536189
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時(shí)間： 2013-10-22
上傳用戶：aeiouetla
21天學(xué)會(huì)用JAVA開發(fā)網(wǎng)絡(luò)游戲 書籍語(yǔ)言： 簡(jiǎn)體中文 書籍類型： 程序設(shè)計(jì) 授權(quán)方式： 免費(fèi)軟件 書籍大?。?287 KB 書籍等級(jí)： 整理時(shí)間： 2004-11-3 20:41:10 With all of the media attention that is focused on the Internet and the World Wide Web, figuring out exactly what they are all about is sometimes difficult. Are they just a neat new way to market products or will they truly offer us a new medium of communication that will someday surpass even televisions and telephones? The answer is, who knows? Unfortunately, the ultimate use for the Internet is still unknown. This is because it is still in such a state of flux that it s pretty much impossible to accurately predict where it will end up. However, you can look at the evidence of what is there now and gain some insight into what the Internet might become, at least in terms of games.
上傳時(shí)間： 2013-12-20
上傳用戶：天誠(chéng)24
物流分析工具包。Facility location: Continuous minisum facility location, alternate location-allocation (ALA) procedure, discrete uncapacitated facility location Vehicle routing: VRP, VRP with time windows, traveling salesman problem (TSP) Networks: Shortest path, min cost network flow, minimum spanning tree problems Geocoding: U.S. city or ZIP code to longitude and latitude, longitude and latitude to nearest city, Mercator projection plotting Layout: Steepest descent pairwise interchange (SDPI) heuristic for QAP Material handling: Equipment selection General purpose: Linear programming using the revised simplex method, mixed-integer linear programming (MILP) branch and bound procedure Data: U.S. cities with populations of at least 10,000, U.S. highway network (Oak Ridge National Highway Network), U.S. 3- and 5-digit ZIP codes
標(biāo)簽： location location-allocation Continuous alternate
上傳時(shí)間： 2015-05-17
上傳用戶：kikye
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
標(biāo)簽： the 20060125 project WinAVR
上傳時(shí)間： 2014-10-10
上傳用戶：yan2267246
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
