s3c2440 backlight driver.SAMSUNG s S3C2440A 16/32-bit RISC microprocessor. SAMSUNG鈥檚 S3C2440A is
designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller
solution in small die size.
This paper shows the development of a 1024-point
radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis
applications.
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device鈥檚
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where lowpower
and low-voltage operation are essential. The devices are available in spacesaving
8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available
in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They
also have a 128-byte page programming function to make their write operation faster.
Note: Renesas Technology鈥檚 serial EEPROM are authorized for using consumer applications such as
cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology鈥檚
sales office before using industrial applications such as automotive systems, embedded controllers,
and meters
A combined space鈥搕ime block coding (STBC) and eigen-space tracking
(EST) scheme in multiple-input-multiple-output systems is
proposed. It is proved that the STBC-EST is capable of shifting
hardware complexity from the receiver to the transmitter without
any bit error rate (BER) performance loss. A computation efficient
EST algorithm is also proposed, which makes the STBC-EST affordable.
Simulation results show that the STBC-EST with a modest
feedback requirement results in a negligible BER performance loss
compared with a dual system configuration.
An interactive water fountain.
A realistic water source in your pocket with full control.
Controls:
UP/DOWN - go closer/further
LEFT/RIGHT - rotate
# - stop rotation
1/7 - rotate camera up/down
3/9 - change water pressure
4/6 - change water rendering complexity
2/8 - ascend/descend
0 - bullet time
5 - 25 FPS limiter on/off
* - HUD on/off
Face Recognition Library
========================
Advanced face recognition DLL using two functions : Train and Recognize. Uses neural net back propogation alogorithm with more AI tools added for imaging optimization. Library works great even for a low resolution web cam image and requires the user to align to a mirror frame on screen. Complete Source Code with Video capture and feature extraction kit for Registered Users.
Please register here for only $299 with Source Code :
http://www.research-lab.com/facerecognitionorder.htm
(c) www.research-lab.com
This software allows users to see how a serial async com port can be used to comunicate with a sync device (SPI). In this case, the software reads a low cost digital temperature sensor IC.
This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting
coding, including finite field arithmetic, (Generalized) Low-Density Parity-
Check (LDPC) codes, and Reed-Solomon codes.
Heapsort
1.A heap is a binary tree satisfying the followingconditions:
-This tree is completely balanced.
-If the height of this binary tree is h, then leaves can be at level h or level h-1.
-All leaves at level h are as far to the left as possible.
-The data associated with all descendants of a node are smaller than the datum associated with this node.
Implementation
1.using a linear array not a binary tree.
-The sons of A(h) are A(2h) and A(2h+1).
2.time complexity: O(n log n)
