The DSPLIB is a collection of 39 high-level optimized DSP functions for the TMS320C64x device. This source code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions.
標(biāo)簽： collection high-level functions optimized
上傳時(shí)間： 2016-10-16
上傳用戶：gengxiaochao
The MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E are low-power transceivers for RS-485 and RS-422 communications in harsh environments. Each driver output and receiver input is protected against ±15kV electrostatic discharge (ESD) shocks, without latchup. These parts contain one driver and one receiver. The MAX483E, MAX487E, MAX488E, and MAX489E feature reduced slewrate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, thus allowing error-free data transmission up to 250kbps. The driver slew rates of the MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E are not limited, allowing them to transmit up to 2.5Mbps.
標(biāo)簽： MAX transceivers 485 low-power
上傳時(shí)間： 2013-12-22
上傳用戶：小寶愛考拉
TL062/TL064 MOTOROLA開發(fā)的low power JFET input operational amplifiers
標(biāo)簽： operational amplifiers MOTOROLA input
上傳時(shí)間： 2016-10-24
上傳用戶：hwl453472107
John Wiley 的書 Rf Technologies For Low Power Wireless Communications，低功耗通信的射頻技術(shù)，非常有意義的一本書
標(biāo)簽： Communications Technologies Wireless Wiley
上傳時(shí)間： 2014-01-16
上傳用戶：nanxia
iic總線控制器VHDL實(shí)現(xiàn) -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
標(biāo)簽： VHDL c_control vhd control
上傳時(shí)間： 2016-10-30
上傳用戶：woshiayin
A Low-Power ASIC Implementation of 2Mbps Antenna-Rake Combiner for WCDMA with MRC and LMS Capabilities.pdf
標(biāo)簽： Implementation Antenna-Rake Capabiliti Low-Power
上傳時(shí)間： 2013-12-16
上傳用戶：yuzsu
Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
標(biāo)簽： Lab Shifter Verilog Design
上傳時(shí)間： 2016-12-01
上傳用戶：cylnpy
ADPLL of high level phase locked loop
標(biāo)簽： locked ADPLL level phase
上傳時(shí)間： 2016-12-04
上傳用戶：wpwpwlxwlx
MATLAB is a high-level language for technical computing which is often used by engineers to help them design systems or analyse a system’s behaviour.
標(biāo)簽： high-level computing engineers technical
上傳時(shí)間： 2014-01-11
上傳用戶：txfyddz
Newnes.Digital.Signal.Processing.System.Level.Design.Using.LabVIEW.Jun.2005.eBook-DDU labview信號(hào)處理教材。
標(biāo)簽： Processing eBook-DDU Digital LabVIEW
上傳時(shí)間： 2014-01-22
上傳用戶：gundan
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