PCI Arbitor by VHDL
上傳時間： 2013-08-18
上傳用戶：h886166
基于FPGA的PCI接口源代碼及Testbenc
上傳時間： 2013-08-20
上傳用戶：sun_pro12580
基于 MAXII 的CPLD 對mobil dram 的讀寫操作，內帶源碼和測試激勵文件
上傳時間： 2013-08-22
上傳用戶：luopoguixiong
基于 MAXII CPLD的對Compact_Flash的讀寫，擦出操作，內附測試激勵文件
標簽： Compact_Flash MAXII CPLD 讀寫
上傳時間： 2013-08-22
上傳用戶：vodssv
基于MAXII CPLD的對1602字符型液晶進行讀寫操作，其中使用了一個CFI的IP核
上傳時間： 2013-08-23
上傳用戶：yeling1919
用vhdl編寫的pci源代碼。花了我2000多元錢買來的，編譯通過！
上傳時間： 2013-08-29
上傳用戶：brilliantchen
PCI是一種高性能的局部總線規范，可實現各種功能標準的PCI總線卡。本文簡要介紹了PCI總線的特點、信號與命令，提出了一種利用高速FPGA實現PCI總線接口的設計方案。\r\n
上傳時間： 2013-08-30
上傳用戶：brain kung
基于FPGA的PCI總線接口的設計方案\r\n~！
上傳時間： 2013-09-01
上傳用戶：heart520beat
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標簽： Architecture ExpressTM PCI
上傳時間： 2013-11-03
上傳用戶：gy592333
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
