1.增加的設(shè)備支持： Atmel AT91SAM9Rxx Cirrus Logic CS7401xx-IQZ Luminary Micro LM3S576x, LM3S5752, LM3S5747, LM3S573x, LM3S5662, LM3S5652, LM3S5632, LM3S3759, LM3S3749, and LM3S3739 NXP LPC32XX and LPC2460 STMicroelectronics STR912FAZ4X, STR912FAW4X, STR911FAW4X, STR911FAM4X, STR910FAW32, and STR910FAZ32 2.修改了NXP LPC23XX/24XX的頭文件庫 3.增加了ST-LINK II的調(diào)試支持 4.增加了對Cortex-M3 內(nèi)核芯片的RTX Event Viewer 的支持 5.增加了MCBSTM32: STM32 FLASH OPTION BYTES PROGRAMMING 6.增加了ULINK2對Cortex-M3的SWV功能的調(diào)試 7.增強(qiáng)了使用GNU在MDK下調(diào)試M1,M3,ARM7,ARM9的調(diào)試功能（ Using μVision with CodeSourcery GNU ARM Toolchain.） 8.增加了大量經(jīng)典開發(fā)板例程 Boards目錄列表： ├─Embest 深圳市英蓓特公司開發(fā)板例程 │ ├─AT91EB40X-40008 │ ├─S3CEB2410 │ ├─ATEBSAM7S │ ├─LPC22EB06-I │ ├─LPCEB2000-A │ ├─LPCEB2000-B │ ├─LPCEB2000-S │ ├─str710 │ ├─str711 │ ├─str730 │ ├─str750 │ ├─STR912 │ ├─STM32V100 │ ├─STM32R100 │ ├─ATEB9200 ├─ADI ADI半導(dǎo)體的芯片例程 │ ├─ADuC702X │ └─ADuC712x ├─Atmel Atmel半導(dǎo)體的芯片例程 │ ├─AT91RM9200-EK │ ├─AT91SAM7A3-EK │ ├─AT91SAM7S-EK │ ├─AT91SAM7SE-EK │ ├─AT91SAM7X-EK │ ├─AT91SAM9260-EK │ ├─AT91SAM9261-EK │ ├─AT91SAM9263-EK ├─Keil Keil公司的開發(fā)板例程 │ ├─MCB2100 │ ├─MCB2103 │ ├─MCB2130 │ ├─MCB2140 │ ├─MCB2300 │ ├─MCB2400 │ ├─MCB2900 │ ├─MCBLM3S │ ├─MCBSTM32 │ ├─MCBSTR7 │ ├─MCBSTR730 │ ├─MCBSTR750 │ └─MCBSTR9 ├─Luminary Luminary半導(dǎo)體公司的芯片例程 │ ├─ek-lm3s1968 │ ├─ek-lm3s3748 │ ├─ek-lm3s3768 │ ├─dk-lm3s101 │ ├─dk-lm3s102 │ ├─dk-lm3s301 │ ├─dk-lm3s801 │ ├─dk-lm3s811 │ ├─dk-lm3s815 │ ├─dk-lm3s817 │ ├─dk-lm3s818 │ ├─dk-lm3s828 │ ├─ek-lm3s2965 │ ├─ek-lm3s6965 │ ├─ek-lm3s811 │ └─ek-lm3s8962 ├─NXP NXP半導(dǎo)體公司的芯片例程 │ ├─LH79524 │ ├─LH7A404 │ └─SJA2510 ├─OKI OKI半導(dǎo)體公司的芯片例程 │ ├─ML674000 │ ├─ML67Q4003 │ ├─ML67Q4051 │ ├─ML67Q4061 │ ├─ML67Q5003 │ └─ML69Q6203 ├─Samsung Samsung半導(dǎo)體公司的芯片例程 │ ├─S3C2440 │ ├─S3C44001 │ └─S3F4A0K ├─ST ST半導(dǎo)體公司的芯片例程 │ ├─CQ-STARM2 │ ├─EK-STM32F │ ├─STM32F10X_EVAL │ ├─STR710 │ ├─STR730 │ ├─STR750 │ ├─STR910 │ └─STR9_DONGLE ├─TI TI半導(dǎo)體公司的芯片例程 │ ├─TMS470R1A256 │ └─TMS470R1B1M ├─Winbond Winbond半導(dǎo)體公司的芯片例程 │ └─W90P710 └─ ...
上傳時(shí)間： 2013-10-13
上傳用戶：zhangliming420
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽： Cortex-M 1850 LPC 內(nèi)核微控制器
上傳時(shí)間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時(shí)間： 2013-10-28
上傳用戶：15501536189
On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash memory.
標(biāo)簽： 1300 LPC 勘誤 數(shù)據(jù)手冊
上傳時(shí)間： 2013-12-13
上傳用戶：lmq0059
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽： 時(shí)鐘恢復(fù) 英文
上傳時(shí)間： 2013-10-30
上傳用戶：ysjing
MAXQUSBJTAGOW評估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽： MAXQUSBJTAGOW 評估板 軟件
上傳時(shí)間： 2013-10-24
上傳用戶：teddysha
SWIFT 提供的服務(wù) 1、接入服務(wù) SWIFT的接入服務(wù)通過SWIFTAlliance的系列產(chǎn)品完成，包括： ?。?） SWIFTAlliance Access and Entry：傳送FIN信息的接口軟件； （2） SWIFTAlliance Gateway：接入SWIFTNet的窗口軟件； ?。?） SWIFTAlliance Webstation：接入SWIFTNet的桌面接入軟件； ?。?） File Transfer Interface：文件傳輸接口軟件，通過SWIFTNet FileAct是用戶方便的訪問其后臺辦公系統(tǒng)。 SWIFTNET Link軟件內(nèi)嵌在SWIFTAlliance Gateway和SWIFTAlliance Webstation中，提供傳輸、標(biāo)準(zhǔn)化、安全和管理服務(wù)。連接后，它確保用戶可以用同一窗口多次訪問SWIFTNet，獲得不同服務(wù)。
標(biāo)簽： SWIFT 設(shè)計(jì)軟件
上傳時(shí)間： 2014-12-03
上傳用戶：huyiming139
MAXQUSBJTAGOW評估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽： MAXQUSBJTAGOW 評估板 軟件
上傳時(shí)間： 2013-11-23
上傳用戶：truth12
Altium Designer10軟件+視頻教程+常用元器件原理圖庫+常用PCB庫下載地址： http://pan.baidu.com/share/link?shareid=463765&uk=572810838 歡迎大家加入電子愛好者群 286744774。
上傳時(shí)間： 2013-11-21
上傳用戶：66666
怎樣使用Nios II處理器來構(gòu)建多處理器系統(tǒng) Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上傳時(shí)間： 2013-11-21
上傳用戶：lo25643
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