Atmel’s AT91SAM7FP105 is a low pincount FingerChip processor based on the 32-bit ARM
RISC processor. It features a on-chip biometric engine performing enrollment verification and
identification, an internal record cache of up to 25 records and a secure command protocol over
USB, SPI, UART. This protocol enables an external host system or processor to control the onchip
bioengine functions, manipulate the record cache, and securely export record cache
records for external storage. Together with the FingerChip sensor device AT77C104B, it forms
an embedded, secured biometric turnkey solution.
After the successful global introduction during the past decade of the second generation (2G) digital
mobile communications systems, it seems that the third generation (3G) Universal Mobile Communication
System (UMTS) has finally taken off, at least in some regions. The plethora of new services that
are expected to be offered by this system requires the development of new paradigms in the way scarce
radio resources should be managed. The Quality of Service (QoS) concept, which introduces in a natural
way the service differentiation and the possibility of adapting the resource consumption to the specific
service requirements, will open the door for the provision of advanced wireless services to the mass
market.
H.264/AVC, the result of the collaboration between the ISO/IEC
Moving Picture Experts Group and the ITU-T Video Coding
Experts Group, is the latest standard for video coding. The goals
of this standardization effort were enhanced compression efficiency,
network friendly video representation for interactive
(video telephony) and non-interactive applications (broadcast,
streaming, storage, video on demand). H.264/AVC provides
gains in compression efficiency of up to 50％ over a wide range
of bit rates and video resolutions compared to previous standards.
Compared to previous standards, the decoder complexity
is about four times that of MPEG-2 and two times that of
MPEG-4 Visual Simple Profile. This paper provides an overview
of the new tools, features and complexity of H.264/AVC.
The Cyclone® III PCI development board provides a hardware platform for developing and
prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a
high-density of the memory to facilitate the design and development of FPGA designs which need
huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of
the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
