Wallace Tree MuLTIplier in VHDL for 4bit operation fully using structural language
標(biāo)簽： MuLTIplier structural operation language
上傳時間： 2014-01-04
上傳用戶：hfmm633
MuLTIplier BCD - vhdl
標(biāo)簽： MuLTIplier vhdl BCD
上傳時間： 2013-12-27
上傳用戶：dongbaobao
complement of MuLTIplier
標(biāo)簽： complement MuLTIplier of
上傳時間： 2013-12-22
上傳用戶：helmos
6x6 bit digital MuLTIplier
標(biāo)簽： MuLTIplier digital 6x6 bit
上傳時間： 2014-01-05
上傳用戶：bruce
Radix 4 Booth MuLTIplier
標(biāo)簽： MuLTIplier Radix Booth
上傳時間： 2017-09-19
上傳用戶：zhuimenghuadie
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth MuLTIplier
標(biāo)簽： Counterflow-Pipelined Asynchronous MuLTIplier Scalable
上傳時間： 2014-01-04
上傳用戶：jjj0202
鎖定放大是微弱信號檢測的重要手段。基于相關(guān)檢測理論，利用開關(guān)電容的開關(guān)實現(xiàn)鎖定放大器中乘法器的功能，提出開關(guān)電容和積分器相結(jié)合以實現(xiàn)相關(guān)檢測的方法，并設(shè)計出一種鎖定放大器。該鎖定放大器將微弱信號轉(zhuǎn)化為與之相關(guān)的方波，通過后續(xù)電路得到正比于被測信號的直流電平，為后續(xù)采集處理提供方便。測量數(shù)據(jù)表明鎖定放大器前級可將10-6 A的電流轉(zhuǎn)換為10-1 V的電壓，后級通過帶通濾波器級聯(lián)可將信號放大1×105倍。該方法在降低噪聲的同時，可對微弱信號進(jìn)行放大，線性度較高、穩(wěn)定性較好。 Abstract: Lock-in Amplifying（LIA）is one of important means for weak signal detection. Based on cross-correlation detection theory， switch in the swithched capacitor was used as MuLTIplier of LIA， and a new method of correlation detection was proposed combining swithched capacitor with integrator. A kind of LIA was designed which can convert the weak signal to square-wave， then DC proportional to measured signal was obtained through follow-up conditioning circuit， providing convenience for signal acquisition and processing. The measured data shows that the electric current（10-6 A） can be changed into voltage（10-1 V） by LIA， and the signal is magnified 1×105 times by cascade band-pass filter. The noise is suppressed and the weak signal is amplified. It has the advantages of good linearity and stability.
標(biāo)簽： 開關(guān)電容 鎖定放大器
上傳時間： 2013-11-29
上傳用戶：黑漆漆
FEATURES400 MSPS internal clock speedIntegrated 10-bit DAC32-bit tuning wordPhase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)Excellent dynamic performance>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUTSerial I/O control1.8 V power supplySoftware and hardware controlled power-down48-lead TQFP/EP packageSupport for 5 V input levels on most digital inputsPLL REFCLK MuLTIplier (4× to 20×)Internal oscillator; can be driven by a single crystalPhase modulation capabilityMultichip synchronization
上傳時間： 2014-12-04
上傳用戶：axin881314
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實現(xiàn)方法，推導(dǎo)出一種簡便的引入?仔/4固定相移的實現(xiàn)方法。采用模塊化的設(shè)計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實現(xiàn)了整個系統(tǒng)。測試結(jié)果表明該系統(tǒng)正確實現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core MuLTIplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時間： 2013-11-06
上傳用戶：liu123
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實現(xiàn)方法，推導(dǎo)出一種簡便的引入?仔/4固定相移的實現(xiàn)方法。采用模塊化的設(shè)計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實現(xiàn)了整個系統(tǒng)。測試結(jié)果表明該系統(tǒng)正確實現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core MuLTIplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時間： 2013-11-19
上傳用戶：neu_liyan
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