c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlying assumption that there are possibly distinct network paths between a source-destination pair. Given a directed graph as input, write a program that uses depth-first search to determine all such paths. Note that, these paths are not vertex-disjoint i.e., the vertices may repeat but they are all edge-disjoint i.e., no two paths have the same edges. The input is the adjacency matrix of a directed acyclic graph and a pair(s) of source and destination vertices and the output should be the number of such disjoint paths and the paths themselves on separate lines. In case of multiple paths the output should be in order of paths with minimum vertices first. In case of tie the vertex number should be taken in consideration for ordering.
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a program that reads in a vertex number and lists the number of edge disjoint cycles that start and end at this vertex. The output should also list the edges in each of the cycle discovered. Input will be the adjacency matrix preceded by a 0 or 1 representing Directed or Undirected graphs respectively.
full wave rectifierDuring the period from 偽 to 蟺, the input voltage vs input current is are positive and the power flows from supply to the load. The converter is said to be operated at rectification mode .During the period from 蟺 to 蟺+偽 , the input voltage vs is negative and the input current is is positive and reverse power flows from load to the supply. The converter is said to be operated in inversion mode. Depending on the value of 偽, average output voltage can be either positive or negative and hence provides 2 quadrant operation.
contains documents related to adaptive beamforming algorithms for Wideband Code Division multiple access and a research article on circular patch antenna for C band altimeter system
The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
This is an interface program for flip flop emulation. At first pulse at the input pin the apropriate output will latch and at the second pulse will release. Very short and efficient program
