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OPERATION-centric

  • Wide Area Monitoring, Protection

    Today, electric power transmission systems should face many demanding chal- lenges, which include balancing between reliability, economics, environmental, and other social objectives to optimize the grid assets and satisfy the growing electrical demand. Moreover, the operational environment of transmission systems is becoming increasingly rigorous due to continually evolving functions of interconnected power networks from operation jurisdiction to control responsibly – coupled with the rising demand and expectation for reliability.

    標(biāo)簽: Monitoring Protection Wide Area

    上傳時(shí)間: 2020-06-07

    上傳用戶:shancjb

  • The Internet of Things From RFI

    With more than two billion terminals in commercial operation world-wide, wire- less and mobile technologies have enabled a first wave of pervasive communication systems and applications. Still, this is only the beginning as wireless technologies such as RFID are currently contemplated with a deployment potential of tens of billions of tags and a virtually unlimited application potential. A recent ITU report depicts a scenario of “Internet of things” — a world in which billions of objects will report their location, identity, and history over wireless connections.

    標(biāo)簽: Internet Things From The RFI of

    上傳時(shí)間: 2020-06-08

    上傳用戶:shancjb

  • Fundamentals_of_Global_Positioning_System1

    The purpose of this book is to present detailed fundamental information on a global positioning system (GPS) receiver. Although GPS receivers are popu- larly used in every-day life, their operation principles cannot be easily found in one book. Most other types of receivers process the input signals to obtain the necessary information easily, such as in amplitude modulation (AM) and frequency modulation (FM) radios. In a GPS receiver the signal is processed to obtain the required information, which in turn is used to calculate the user position. Therefore, at least two areas of discipline, receiver technology and navigation scheme, are employed in a GPS receiver. This book covers both areas.

    標(biāo)簽: Fundamentals_of_Global_Positionin g_System_Receivers

    上傳時(shí)間: 2020-06-09

    上傳用戶:shancjb

  • Modern_Control_Theory

    The main aim of this book is to present a unified, systematic description of basic and advanced problems, methods and algorithms of the modern con- trol theory considered as a foundation for the design of computer control and management systems. The scope of the book differs considerably from the topics of classical traditional control theory mainly oriented to the needs of automatic control of technical devices and technological proc- esses. Taking into account a variety of new applications, the book presents a compact and uniform description containing traditional analysis and op- timization problems for control systems as well as control problems with non-probabilistic models of uncertainty, problems of learning, intelligent, knowledge-based and operation systems – important for applications in the control of manufacturing processes, in the project management and in the control of computer systems.

    標(biāo)簽: Modern_Control_Theory

    上傳時(shí)間: 2020-06-10

    上傳用戶:shancjb

  • 基于界面操作的人臉心率檢測的代碼

    基于界面操作的人臉心率檢測的代碼,通過攝像頭實(shí)時(shí)采集人視頻,并計(jì)算心率(Face the heart rate detection interface operation based on the code, through real-time acquisition one camera video, and rate)

    標(biāo)簽: 操作 人臉 代碼 檢測

    上傳時(shí)間: 2021-02-24

    上傳用戶:

  • LLC 電路基本原理分析及公式推導(dǎo).pdf

    ? LLC series-resonant Half-bridge: operationand significant waveforms? Simplified model (FHA approach)? 300W design example

    標(biāo)簽: llc 電路原理

    上傳時(shí)間: 2021-11-22

    上傳用戶:

  • DDR4標(biāo)準(zhǔn) JESD79_4

    1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34

    標(biāo)簽: DDR4

    上傳時(shí)間: 2022-01-09

    上傳用戶:

  • 高通(Qualcomm)藍(lán)牙芯片QCC5151_硬件設(shè)計(jì)詳細(xì)指導(dǎo)書(官方內(nèi)部培訓(xùn)手冊(cè))

    高通(Qualcomm)藍(lán)牙芯片QCC5151_硬件設(shè)計(jì)詳細(xì)指導(dǎo)書(官方內(nèi)部培訓(xùn)手冊(cè))共52頁其內(nèi)容是針對(duì)硬件設(shè)計(jì)、部分重要元器件選擇(ESD,F(xiàn)ilter)及走線注意事項(xiàng)的詳細(xì)說明。2 Power management 2.1 SMPS 2.1.1 Components specification 2.1.2 Input power supply selection 2.1.3 Minimize SMPS EMI emissions 2.1.4 Internal LDOs and digital core decoupling 2.1.5 Powering external components 2.2 Charger 2.2.1 Charger connections.2.2.2 General charger operation2.2.3 Temperature measurement during charging 2.3 SYS_CTRL 3 Bluetooth radio3.1 RF PSU component choice 3.2 RF band-pass filter3.3 Layout (天線 走線的注意事項(xiàng))4 Audio4.1 Audio bypass capacitors 4.2 Earphone speaker output4.3 Line/Mic input 4.4 Headphone output optimizition5 LED pads 5.1 LED driver 5.2 Digital/Button input 5.3 Analog input5.4 Disabled 6 Reset pin (Reset#)7 QSPIinterface 8 USB interfaces 8.1 USB device port8.1.1 USB connections8.1.2 Layout notes8.1.3 USB charger detection

    標(biāo)簽: qualcomm 藍(lán)牙芯片 qcc5151

    上傳時(shí)間: 2022-01-24

    上傳用戶:XuVshu

  • SI2302_2.0.pdf規(guī)格書下載

    The SI2302 uses advanced trench technology to provide excellent RDS(ON), low gate charge andoperation with gate voltages as low as 2.5V. This device is suitable for use as a Battery protection orin other Switching application

    標(biāo)簽: si2302

    上傳時(shí)間: 2022-02-11

    上傳用戶:

  • PW4055_2.0.pdf規(guī)格書下載

    The PW4055 is a complete constant-current /constant-voltage linear charger for single cell lithiumion batteries.Its ThinSOT package and low external component count make the PW4055 ideallysuited for portable applications.Furthermore, the PW4055 is specifically designed to work within USBpower specifications.The PW4055 No external sense resistor is needed, and no blocking diode is required due to theinternal MOSFET architecture.Thermal feedback regulates the charge current to limit the dietemperature during high power operation or high ambient temperature. The charge voltage is fixedat 4.2V, and the charge current can be programmed externally with a single resistor. The PW4055automatically terminates the charge cycle when the charge current drops to 1/10th the programmedvalue after the final float voltage is reached. When the input supply (wall adapter or USB supply) isremoved, the PW4055 automatically enters a low current state, dropping the battery drain currentto less than 2μA. The PW4055 can be put into shutdown mode, reducing the supply current to 25μA.The BAT pin has a 7KV ESD(HBM) capability. Other features include charge current monitor, undervoltage lockout, automatic recharge and a status pin to indicate charge termination and the presenceof an input voltage

    標(biāo)簽: pw4055

    上傳時(shí)間: 2022-02-11

    上傳用戶:jason_vip1

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