Abstract: This application note explains the hardware of different types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two different types: 5V general interface and 12V RS-232 interface. Within the 5V group a common printed circuit board could be used for all circuits described. The variations can be achieved by different populations of components. The same principal is used for the 12V RS-232 interface. The population determines if it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many different configurations. For a custom application, one of the described Options can be adapted to meet individual needs.
標(biāo)簽： iButtons Reading Writing and
上傳時(shí)間： 2013-10-29
上傳用戶：long14578
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of Options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時(shí)間： 2013-11-19
上傳用戶：yyyyyyyyyy
The CodeWarrior Development Suite provides access and technical support to amultitude of CodeWarrior products. In this quick start guide, Section 1 explains howto register your CodeWarrior Development Suite. Section 2 explains how to activateand install one of your products. Section 3 describes what you are entitled to withthe purchase of your CodeWarrior Development Suite, and Section 4 discusses theavailable purchase Options. Section 5 describes the benefits of maintaining a currenttechnical support contract, and Section 6 tells you how to access support.
標(biāo)簽： CodeWarrior 開(kāi)發(fā)套件
上傳時(shí)間： 2014-03-02
上傳用戶：784533221
用MDK 生成bin 文件1用MDK 生成bin 文件Embest 徐良平在RV MDK 中，默認(rèn)情況下生成*.hex 的可執(zhí)行文件，但是當(dāng)我們要生成*.bin 的可執(zhí)行文件時(shí)怎么辦呢？答案是可以使用RVCT 的fromelf.exe 工具進(jìn)行轉(zhuǎn)換。也就是說(shuō)首先將源文件編譯鏈接成*.axf 的文件，然后使用fromelf.exe 工具將*.axf 格式的文件轉(zhuǎn)換成*.bin格式的文件。下面將具體說(shuō)明這個(gè)操作步驟：1. 打開(kāi)Axf_To_Bin 文件中的Axf_To_Bin.uv2 工程文件；2. 打開(kāi)Options for Target ‘Axf_To_Bin’對(duì)話框，選擇User 標(biāo)簽頁(yè)；3. 構(gòu)選Run User Programs After Build/Rebuild 框中的Run #1 多選框，在后邊的文本框中輸入C:\Keil\ARM\BIN31\fromelf.exe --bin -o ./output/Axf_To_Bin.bin ./output/Axf_To_Bin.axf 命令行；4. 重新編譯文件，在./output/文件夾下生成了Axf_To_Bin.bin 文件。在上面的步驟中，有幾點(diǎn)值得注意的是：1. C:\Keil\ARM\BIN31\表示RV MDK 的安裝目錄；2. fromelf.exe 命令的具體語(yǔ)法格式如下：命令的格式為：fromelf [Options] input_file命令選項(xiàng)如下：--help 顯示幫助信息--vsn 顯示版本信息--output file 輸出文件(默認(rèn)的輸出為文本格式)--nodebug 在生成的映象中不包含調(diào)試信息--nolinkview 在生成的映象中不包含段的信息二進(jìn)制輸出格式：--bin 生成Plain Binary 格式的文件--m32 生成Motorola 32 位十六進(jìn)制格式的文件--i32 生成Intel 32 位十六進(jìn)制格式的文件--vhx 面向字節(jié)的位十六進(jìn)制格式的文件t--base addr 設(shè)置m32，i32 格式文件的基地址--text 顯示文本信息文本信息的標(biāo)志-v 打印詳細(xì)信息-a 打印數(shù)據(jù)地址(針對(duì)帶調(diào)試信息的映象)-d 打印數(shù)據(jù)段的內(nèi)容-e 打印表達(dá)式表print exception tables-f 打印消除虛函數(shù)的信息-g 打印調(diào)試表print debug tables-r 打印重定位信息-s 打印字符表-t 打印字符串表-y 打印動(dòng)態(tài)段的內(nèi)容-z 打印代碼和數(shù)據(jù)大小的信息
標(biāo)簽： MDK bin 可執(zhí)行文件
上傳時(shí)間： 2013-12-17
上傳用戶：AbuGe
Abstract: The process of designing a radio system can be complex and often involves many project tradeoffs. Witha little insight, balancing these various characteristics can make the job of designing a radio system easier. Thistutorial explores these tradeoffs and provides details to consider for various radio applications. With a focus on theindustrial, scientific, medical (ISM) bands, the subjects of frequency selection, one-way versus two-way systems,modulation techniques, cost, antenna Options, power-supply influences, effects on range, and protocol selectionare explored.
標(biāo)簽： 無(wú)線
上傳時(shí)間： 2013-12-13
上傳用戶：eastgan
Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of Options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
標(biāo)簽： 492 DN 降壓 溫度監(jiān)控
上傳時(shí)間： 2014-01-03
上傳用戶：Huge_Brother
§1、安裝： SPB15.2 CD1～3，安裝1、2，第3為庫(kù)，不安裝 License安裝： 設(shè)置環(huán)境變量lm_license_file D:\Cadence\license.dat 修改license中SERVER yyh ANY 5280為SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)設(shè)計(jì)原理圖 進(jìn)入Design Entry CIS Studio 設(shè)置操作環(huán)境\Options\Preferencses: 顏色：colors/Print 格子：Grid Display 雜項(xiàng)：Miscellaneous .........常取默認(rèn)值
上傳時(shí)間： 2013-11-13
上傳用戶：wangchong
西門(mén)子PLC S7-200編程軟件最新版本(2012.3) STEP7 MicroWIN_V4 SP9 完整版, 全面支持Windows7。安裝完后，打開(kāi)軟件，初次為英文版，點(diǎn)擊tools（左上角自左-右第6個(gè)）然后選擇最下面的Options（自上而下第15個(gè)）單擊，出現(xiàn)又一個(gè)畫(huà)面，在左邊選擇第一個(gè)選項(xiàng)General，就出現(xiàn)了語(yǔ)言選項(xiàng)，選擇最下面的那個(gè)（Chinese）也就是中文。然后點(diǎn)擊OK按鈕，然后一路回車下去，直到軟件關(guān)閉，再打開(kāi)時(shí)就是中文的啦！
上傳時(shí)間： 2013-11-19
上傳用戶：mikesering
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) Options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上傳時(shí)間： 2014-01-11
上傳用戶：a471778
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation Options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上傳時(shí)間： 2013-12-14
上傳用戶：逗逗666
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