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DS+DDK+VC開發(fā)的適用于PCI、PCI-E的驅(qū)動程序。
上傳時間： 2014-01-19
上傳用戶：蠢蠢66
Windows下讀寫硬件的工具. RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, Memory Index/Data, I/O Space, I/O Index/Data, Super I/O, Clock Generator, DIMM SPD, SMBus Device, CPU MSR Registers, ATA/ATAPI Identify Data, ACPI Tables Dump (include AML decode), Embedded Controller, USB Information and LPT Remote Access. And also an Command Window is provided to access hardware manually.
標(biāo)簽： engineers firmware hardware Windows
上傳時間： 2015-07-01
上傳用戶：xc216
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, Memory Index/Data, I/O Space, I/O Index/Data, Super I/O, Clock Generator, DIMM SPD, SMBus Device, CPU MSR Registers, ATA/ATAPI Identify Data, ACPI Tables Dump (include AML decode), Embedded Controller, USB Information and LPT Remote Access. And also an Command Window is provided to access hardware manually. Website1: http://rw.net-forces.com/ Website2: http://home.kimo.com.tw/ckimchan.tw/ Website3: http://jacky5488.myweb.hinet.net/ For best view, please change the screen resolution to 1024 x 768 (or above) pixels.
標(biāo)簽： engineers developers firmware hardware
上傳時間： 2013-12-22
上傳用戶：王楚楚
CPCI_E標(biāo)準(zhǔn)規(guī)范 CompactPCI? Express SpecificationThe documents in this section may be useful for reference when reading the specification. The revision listed for each document is the latest revision at the time this specification was published. Newer revisions of these documents may exist, so refer to the newest revision. Many of these documents are referenced throughout this specification. Refer to the newest revision of the document unless a specific revision is referenced. ? PCI Express Base Specification 3.0. PCI Special Interest Group (PCI-SIG). ? PCI Express Card Electromechanical (CEM) Specification 3.0. PCI Special Interest Group (PCI-SIG). ? PCI Express to PCI/PCI-X Bridge Specification, Rev. 1.0. PCI Special Interest Group (PCI-SIG). ? PCI Express Jitter White Paper. PCI Special Interest Group (PCI-SIG). ? PCIe Rj Dj BER White Paper. PCI Special Interest Group (PCI-SIG). ? PHY Electrical Test Specification for PCI Express Architecture. PCI Special Interest Group (PCI SIG). ? System Management Bus (SMBus) Specification, Version 2.0. Smart Battery System Implementer’
標(biāo)簽： CPCIE
上傳時間： 2022-02-23
上傳用戶：
CH341系列編程器芯片usb轉(zhuǎn)串口Altium Designer AD原理圖庫元件庫CSV text has been written to file : 1.9 - CH341系列編程器芯片.csvLibrary Component Count : 56Name Description----------------------------------------------------------------------------------------------------CH311Q PC debug port monitorCH331T Mini USB Disk ControllerCH340G CH340H USB to TTL Serial / UART, USB to IrDACH340T USB to TTL Serial / UART, USB to IrDACH340R USB to IrDA, USB to RS232 SerialCH340S_P USB to Print Port / ParallelCH340S_S USB to TTL Serial / UART, pin compatible with CH341CH341A_S USB to TTL Serial / UART / I2C/IICCH341S_P USB to Print Port / ParallelCH341A_P USB to Print Port / ParallelCH341S_S USB to TTL Serial / UARTCH341S_X USB to EPP Parallel / SPI / I2C/IICCH341A_X USB to EPP Parallel / SPI / I2C/IICCH341T USB to TTL Serial / UART / I2C/IICCH345T USB to MidiCH352L_M PCI to 8255 mode 2 Parallel for MCU and 16C550 UART / IrDACH352L_P PCI to Print Port / Parallel and 16C550 UART / IrDACH352L_S PCI to Dual 16C550 UART, TTL Serial*2 / IrDA*1CH362L PCI Device / Slave only for RAM / Expansion ROMCH364F Member of CH364 chipsetsCH364P PCI Device / Slave Embedded Flash ROM, for Expansion ROMCH365P PCI Device / Slave, for I/O port or RAM / ROMCH372T USB Device / Slave for MCU, ParallelCH372A USB Device / Slave for MCU, ParallelCH372V USB Device / Slave for MCU, ParallelCH374S USB Host & Device / Slave for MCU, parallel / SPICH374T USB Host & Device / Slave for MCU, parallel / SPICH375S USB Host & Device / Slave for MCU, parallel / UART SerialCH375A USB Host & Device / Slave for MCU, parallel / UART SerialCH375V USB Host & Device / Slave for MCU, parallel / UART SerialCH411G FDC MFM encode and decodeCH421A Dual port bufferCH421S Dual port bufferCH423D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423S I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423D_D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423S_D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423G I2C/IIC I/O expander, 6 GPO + 5 GPIOCH432Q Dual 16C550 UART with IrDA, parallel / SPICH432T SPI Dual 16C550 UART with IrDACH450K 6 Digits / 48 LEDs Drive & 8x6 Keyboard, I2C/IICCH450H 6 Digits / 48 LEDs Drive & 8x6 Keyboard, I2C/IICCH450L 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH451L 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH451S 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH451D 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH452L_2 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH452L_4 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH452S_2 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH452S_4 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH453S 16 Digits / 128 LEDs Drive, I2C/IICCH453D 16 Digits / 128 LEDs Drive, I2C/IICPCI 32Bit PCI Bus, simple / short cardPCI32 32Bit PCI BusUSB USB Port
標(biāo)簽： ch341 編程芯片 usb 串口 altium designer
上傳時間： 2022-03-13
上傳用戶：
pcie基本概念及其工作原理介紹：PCI Express®（或稱PCIe®），是一項高性能、高帶寬，此標(biāo)準(zhǔn)由互連外圍設(shè)備專業(yè)組（PCI-SIG）制 訂，用于替代PCI、PCI Extended (PCI-X)等基于總線的通訊體系架構(gòu)以及圖形加速端口（AGP）。 轉(zhuǎn)向PCIe主要是為了實現(xiàn)顯著增強(qiáng)系統(tǒng)吞吐量、擴(kuò)容性和靈活性的目標(biāo)，同時還要降低制造成本，而這 些都是基于總線的傳統(tǒng)互連標(biāo)準(zhǔn)所達(dá)不到的。PCI Express標(biāo)準(zhǔn)在設(shè)計時著眼于未來，并且能夠繼續(xù)演 進(jìn)，從而為系統(tǒng)提供更大的吞吐量。第一代PCIe規(guī)定的吞吐量是每秒2.5千兆比特（Gbps），第二代規(guī) 定的吞吐量是5.0 Gbps，而最近公布PCIe 3.0標(biāo)準(zhǔn)已經(jīng)支持8.0 Gbps的吞吐量。在PCIe標(biāo)準(zhǔn)繼續(xù)充分利 用最新技術(shù)來提供不斷加大的吞吐量的同時，采用分層協(xié)議也便于PCI向PCIe的演進(jìn)，并保持了與現(xiàn)有 PCI應(yīng)用的驅(qū)動程序軟件兼容性。 雖然最初的目標(biāo)是計算機(jī)擴(kuò)展卡以及圖形卡，但PCIe目前也廣泛適用于涵蓋更廣的應(yīng)用門類，包括網(wǎng)絡(luò) 組建、通信、存儲、工業(yè)電子設(shè)備和消費類電子產(chǎn)品。 本白皮書的目的在于幫助讀者進(jìn)一步了解PCI Express以及成功PCIe成功應(yīng)用。 PCI Express基本工作原理 拓?fù)浣Y(jié)構(gòu) 本節(jié)介紹了PCIe協(xié)議的基本工作原理以及當(dāng)今系統(tǒng)中實現(xiàn)和支持PCIe協(xié)議所需要的各個組成部分。本節(jié) 的目標(biāo)在于提供PCIe的相關(guān)工作知識，并未涉及到PCIe協(xié)議的具體復(fù)雜性。 PCIe的優(yōu)勢就在于降低了復(fù)雜度所帶來的成本。PCIe屬于一種基于數(shù)據(jù)包的串行連接協(xié)議，它的復(fù)雜度 估計在PCI并行總線的10倍以上。之所以有這樣的復(fù)雜度，部分是由于對以千兆級的速度進(jìn)行并行至串 行的數(shù)據(jù)轉(zhuǎn)換的需要，部分是由于向基于數(shù)據(jù)包實現(xiàn)方案的轉(zhuǎn)移。 PCIe保留了PCI的基本載入-存儲體系架構(gòu)，包括支持以前由PCI-X標(biāo)準(zhǔn)加入的分割事務(wù)處理特性。此 外，PCIe引入了一系列低階消息傳遞基元來管理鏈路（例如鏈路級流量控制），以仿真?zhèn)鹘y(tǒng)并行總線的 邊帶信號，并用于提供更高水平的健壯性和功能性。此規(guī)格定義了許多既支持當(dāng)今需要又支持未來擴(kuò)展 的特性，同時還保持了與PCI軟件驅(qū)動程序的兼容性。PCI Express的先進(jìn)特性包括：自主功率管理； 先進(jìn)錯誤報告；通過端對端循環(huán)冗余校驗（ECRC）實現(xiàn)的端對端可靠性，支持熱插拔；以及服務(wù)質(zhì)量（QoS）流量分級。
標(biāo)簽： pcie_cn pcie 基本概念 工作原理
上傳時間： 2013-11-29
上傳用戶：zw380105939
一博科技PCB設(shè)計指導(dǎo)書VER1.0. 66頁常見信號介紹 1.1 數(shù)字信號 1.1.1 CPU 常稱處理器，系統(tǒng)通過數(shù)據(jù)總線、地址總線、控制總線實現(xiàn)處理器、控制芯片、存 儲器之間的數(shù)據(jù)交換。 地址總線：ADD* （如：ADDR1） 數(shù)據(jù)總線：D* （如：SDDATA0） 控制總線：讀寫信號（如：WE_N），片選信號（如：SDCS0_N），地址行列選擇信 號（如：SDRAS_N），時鐘信號（如：CLK），時鐘使能信號（如：SDCKE）等。 與CPU對應(yīng)的存儲器是SDRAM，以及速率較高的DDR存儲器： SDRAM：是目前主推的PC100和PC133規(guī)范所廣泛使用的內(nèi)存類型，它的帶寬為64位， 支持3.3V電壓的LVTTL，目前產(chǎn)品的最高速度可達(dá)5ns。它與CPU使用相同的時鐘頻 率進(jìn)行數(shù)據(jù)交換，它的工作頻率是與CPU的外頻同步的，不存在延遲或等待時間。 SDRAM與時鐘完全同步。 DDR：速率比SDRAM高的內(nèi)存器，可達(dá)到800M，它在時鐘觸發(fā)沿的上、下沿都能進(jìn)行 數(shù)據(jù)傳輸，所以即使在133MHz的總線頻率下的帶寬也能達(dá)到2.128GB/s。它的地址 與其它控制界面與SDRAM相同，支持2.5V/1.8V的SSTL2標(biāo)準(zhǔn). 阻抗控制在50Ω±10 ％. 利用時鐘的邊緣進(jìn)行數(shù)據(jù)傳送的，速率是SDRAM的兩倍. 其時鐘是采用差分方 式。 1.1.2 PCI PCI總線：PCI總線是一種高速的、32/64位的多地址/數(shù)據(jù)線，用于控制器件、外圍 接口、處理器/存儲系統(tǒng)之間進(jìn)行互聯(lián)。PCI 的信號定義包括兩部份(如下圖)：必 須的(左半部份)與可選的（右半部份）。其中“# ”代表低電平有效。
標(biāo)簽： pcb設(shè)計
上傳時間： 2022-02-06
上傳用戶：得之我幸78
write code to read the PCI configuration information, there are two ways.
標(biāo)簽： configuration information write there
上傳時間： 2015-05-09
上傳用戶：chens000
This doecument display that how to access pci configure space
標(biāo)簽： doecument configure display access
上傳時間： 2013-12-19
上傳用戶：windwolf2000
PCI Hot-Plug Specification Revision 1.0 The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI adapter cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms.
標(biāo)簽： Specification specification objective Hot-Plug
上傳時間： 2013-12-09
上傳用戶：zyt
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