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PLB

PLB Block RAM(BRAM)接口控制器

The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).

標簽： Block BRAM PLB RAM

上傳時間： 2013-10-27

上傳用戶：zoudejile
PLB Block RAM(BRAM)接口控制器

The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).

標簽： Block BRAM PLB RAM

上傳時間： 2013-10-27

上傳用戶：Breathe0125
PLB Block RAM(BRAM)接口控制器

基于RAM塊的應用

標簽： Block BRAM PLB RAM

上傳時間： 2013-11-02

上傳用戶：box2000
XAPP806 -決定DDR反饋時鐘的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

標簽： XAPP 806 DDR DCM

上傳時間： 2013-10-15

上傳用戶：euroford
帶有SerDes接口的PLB千兆位級以太網MAC

This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.

標簽： SerDes PLB MAC 接口

上傳時間： 2013-11-01

上傳用戶：truth12
基于SOPC技術的異步串行通信IP核的設計

介紹了SoPC（System on a Programmable Chip）系統的概念和特點，給出了基于PLB總線的異步串行通信（UART）IP核的硬件設計和實現。通過將設計好的UART IP核集成到SoPC系統中加以驗證，證明了所設計的UART IP核可以正常工作。該設計方案為其他基于SoPC系統IP核的開發提供了一定的參考。

標簽： SOPC IP核異步串行通信

上傳時間： 2013-11-12

上傳用戶：894448095
PLB Block RAM(BRAM)接口控制器

基于RAM塊的應用

標簽： Block BRAM PLB RAM

上傳時間： 2015-01-01

上傳用戶：13681659100
XAPP806 -決定DDR反饋時鐘的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

標簽： XAPP 806 DDR DCM

上傳時間： 2014-11-26

上傳用戶：erkuizhang
SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design follo

SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM

標簽： high-level following reference diagram

上傳時間： 2013-12-15

上傳用戶：Miyuki
Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.

標簽： System-on-Chip Microblaze embedded Spartan

上傳時間： 2013-12-20

上傳用戶：上善若水

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PLB

PLB Block RAM(BRAM)接口控制器

PLB Block RAM(BRAM)接口控制器

PLB Block RAM(BRAM)接口控制器

XAPP806 -決定DDR反饋時鐘的最佳DCM相移

帶有SerDes接口的PLB千兆位級以太網MAC

基于SOPC技術的異步串行通信IP核的設計

PLB Block RAM(BRAM)接口控制器

XAPP806 -決定DDR反饋時鐘的最佳DCM相移

SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design follo

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process